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docs: update bazel-orfs.md with build results for 12 new designs
7 of 12 newly enabled designs now pass QoR tests (53 total). 5 designs remain blocked: - 3 on bazel-orfs ADDITIONAL_LEFS bug (black_parrot, bp_multi_top, i2c-gpio-expander) - 1 on yosys check -assert failure (bp_quad) - 1 on missing SV macros in synth (mempool_group) Co-Authored-By: Claude Opus 4.6 (1M context) <[email protected]> Signed-off-by: Øyvind Harboe <[email protected]>
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bazel-orfs.md

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@@ -5,9 +5,9 @@ into OpenROAD-flow-scripts. It lets you build ORFS designs with Bazel
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using the same `config.mk` files you already have.
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**Status**: beta -- 58 designs across 6 public PDK platforms have
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`orfs_design()` enabled. 46 pass QoR tests; 12 newly enabled designs
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need metric thresholds. Platforms without public PDK files (gf12, gf55,
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rapidus2hp) are not wired up.
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`orfs_design()` enabled. 53 pass QoR tests; 5 designs are blocked on
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upstream fixes (see below). Platforms without public PDK files (gf12,
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gf55, rapidus2hp) are not wired up.
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## Quick Start
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@@ -51,11 +51,11 @@ Each enabled design gets these targets automatically from its `config.mk`:
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Each stage depends on the previous one, so building `_final` runs the
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entire flow.
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## Working Designs (46 passing tests + 12 newly enabled)
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## Working Designs (53 passing tests + 5 blocked)
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All designs below have `orfs_design()` enabled. Designs marked
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**(new)** were recently unblocked and need metric threshold tuning
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before `bazelisk test` passes.
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**(blocked)** fail due to upstream issues in bazel-orfs or the
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design's verilog sources.
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### asap7 (17 designs)
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| `mock-cpu` | mock_cpu | mock CPU with FIFO |
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| `swerv_wrapper` | swerv_wrapper | SweRV EH1 |
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| `cva6` | cva6 | CVA6 RISC-V (~63 min) |
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| `mock-alu` | MockAlu | **(new)** mock ALU |
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| `mock-alu` | MockAlu | mock ALU |
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### sky130hd (7 designs)
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| `dynamic_node` | dynamic_node_top_wrap | NoC router |
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| `swerv` | swerv | SweRV EH1 |
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| `tinyRocket` | RocketTile | RISC-V Rocket |
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| `ariane133` | ariane | **(new)** hierarchical |
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| `ariane136` | ariane | **(new)** hierarchical |
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| `black_parrot` | black_parrot | **(new)** hierarchical |
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| `bp_be_top` | bp_be_top | **(new)** BP back-end |
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| `bp_fe_top` | bp_fe_top | **(new)** BP front-end |
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| `bp_multi_top` | bp_multi_top | **(new)** BP multi-core |
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| `bp_quad` | black_parrot | **(new)** BP quad-core |
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| `mempool_group` | mempool_group | **(new)** MemPool group |
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| `swerv_wrapper` | swerv_wrapper | **(new)** SweRV wrapped |
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| `ariane133` | ariane | hierarchical |
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| `ariane136` | ariane | hierarchical |
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| `black_parrot` | black_parrot | **(blocked)** ADDITIONAL_LEFS not loaded |
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| `bp_be_top` | bp_be_top | BP back-end |
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| `bp_fe_top` | bp_fe_top | BP front-end |
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| `bp_multi_top` | bp_multi_top | **(blocked)** ADDITIONAL_LEFS not loaded |
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| `bp_quad` | black_parrot | **(blocked)** yosys check -assert fails |
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| `mempool_group` | mempool_group | **(blocked)** SV macro undefined in synth |
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| `swerv_wrapper` | swerv_wrapper | SweRV wrapped |
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### gf180 (6 designs)
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| `ibex` | ibex_core | RISC-V core |
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| `jpeg` | jpeg_encoder | JPEG encoder |
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| `riscv32i` | riscv | RISC-V RV32I |
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| `uart-blocks` | uart | **(new)** hierarchical with uart_rx block |
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| `uart-blocks` | uart | hierarchical with uart_rx block |
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### ihp-sg13g2 (7 designs)
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| `jpeg` | jpeg_encoder | JPEG encoder |
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| `riscv32i` | riscv | RISC-V RV32I |
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| `spi` | spi | SPI controller |
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| `i2c-gpio-expander` | I2cGpioExpanderTop | **(new)** I2C GPIO with I/O pads |
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| `i2c-gpio-expander` | I2cGpioExpanderTop | **(blocked)** ADDITIONAL_LEFS not loaded |
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### sky130hs (5 designs)
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`MODULE.bazel`.
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- Platforms without public PDK files (gf12, gf55, rapidus2hp) are not
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supported.
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- 12 newly enabled designs need metric threshold tuning (`rules-base.json`).
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- **bazel-orfs ADDITIONAL_LEFS bug**: `ADDITIONAL_LEFS` declared in
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`config.mk` are parsed correctly but not passed to `read_lef` in
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OpenROAD. This blocks 3 designs (black_parrot, bp_multi_top,
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i2c-gpio-expander) that need fakeram or IO pad LEFs.
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- **bp_quad**: yosys `check -assert` finds 9 problems during synthesis.
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- **mempool_group**: SystemVerilog macros (`AXI_TYPEDEF_RESP_T` etc.)
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are undefined -- likely a missing include path in the bazel build.
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- This is a beta -- expect rough edges. File issues at
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https://github.com/The-OpenROAD-Project/bazel-orfs/issues

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