Merge pull request #4130 from The-OpenROAD-Project-staging/switched-inout-to-pct

Switched input/output delay values to a percentage of the clock period

Author: maliberty

flow/designs/rapidus2hp/hercules_idecode/prects_0.3.sdc

@@ -5,6 +5,10 @@ set sdc_version 1.4
 current_design hercules_idecode
 
 set clk_period 370
+# Roughly 150ps for a 370ps clock
+set input_pct 0.4054
+# Roughly 50ps for a 370ps clock
+set output_pct 0.1351
 
 convert_time_value clk_period
 
@@ -18,5 +22,5 @@ create_clock -name "clk" -add -period $clk_period \
 set_clock_latency $clk_period clk
 
 ### Setup input delay is set to 20% of CT
-set_input_delay 0.150 -clock clk [all_inputs]
-set_output_delay 0.050 -clock clk [all_outputs]
+set_input_delay [expr { $clk_period * $input_pct }] -clock clk [all_inputs]
+set_output_delay [expr { $clk_period * $output_pct }] -clock clk [all_outputs]

flow/designs/rapidus2hp/hercules_is_int/prects_0.3.sdc

@@ -5,6 +5,10 @@ set sdc_version 1.4
 current_design hercules_is_int
 
 set clk_period 370
+# Roughly 150ps for a 370ps clock
+set input_pct 0.4054
+# Roughly 50ps for a 370ps clock
+set output_pct 0.1351
 
 convert_time_value clk_period
 
@@ -18,5 +22,5 @@ create_clock -name "clk" -add -period $clk_period \
 set_clock_latency $clk_period clk
 
 ### Setup input delay is set to 20% of CT
-set_input_delay 0.150 -clock clk [all_inputs]
-set_output_delay 0.050 -clock clk [all_outputs]
+set_input_delay [expr { $clk_period * $input_pct }] -clock clk [all_inputs]
+set_output_delay [expr { $clk_period * $output_pct }] -clock clk [all_outputs]