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docs: update bazel-orfs.md with all 46 working designs across 6 platforms
- Replace old 10-design list with full 46-design table across asap7, sky130hd, nangate45, gf180, ihp-sg13g2, sky130hs - Document blocked designs with specific bazel-orfs fixes needed: hierarchical sub-design targets, specific file references, platform-local verilog, generated verilog - Add performance notes on thread overcommitment and --jobs flag - Update known limitations Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com> Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>
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‎bazel-orfs.md‎

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@@ -4,10 +4,9 @@ This is an early integration of [bazel-orfs](https://github.com/The-OpenROAD-Pro
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into OpenROAD-flow-scripts. It lets you build ORFS designs with Bazel
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using the same `config.mk` files you already have.
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**Status**: beta -- all 8 asap7 designs build and pass QoR tests.
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The full patch set lives out-of-tree in `bazel-orfs/orfs/` to minimize
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churn; this PR wires up the minimum needed for developers to kick the
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tires.
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**Status**: beta -- 46 designs across 6 public PDK platforms build and
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pass QoR tests. Platforms without public PDK files (gf12, gf55,
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rapidus2hp) are not wired up.
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## Quick Start
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Each stage depends on the previous one, so building `_final` runs the
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entire flow.
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## Working Designs
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## Working Designs (46 passing tests)
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All designs below have `orfs_design()` enabled and pass
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`bazelisk test` with QoR regression checks.
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### asap7 (16 designs)
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| Design | DESIGN_NAME | Notes |
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|--------|-------------|-------|
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| `gcd` | gcd | smoketest, ~1 min |
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| `gcd-ccs` | gcd | CCS lib model |
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| `aes` | aes_cipher_top | medium |
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| `aes-block` | aes_cipher_top | block variant |
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| `aes-mbff` | aes_cipher_top | MBFF |
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| `aes_lvt` | aes_cipher_top | LVT cells |
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| `ethmac` | ethmac | Ethernet MAC |
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| `ethmac_lvt` | ethmac | LVT cells |
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| `ibex` | ibex_core | RISC-V core (slang) |
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| `jpeg` | jpeg_encoder | JPEG encoder |
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| `jpeg_lvt` | jpeg_encoder | LVT cells |
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| `uart` | uart | UART |
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| `riscv32i` | riscv_top | RISC-V RV32I |
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| `mock-cpu` | mock_cpu | mock CPU with FIFO |
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| `swerv_wrapper` | swerv_wrapper | SweRV EH1 |
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| `cva6` | cva6 | CVA6 RISC-V (~63 min) |
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### sky130hd (7 designs)
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| Design | DESIGN_NAME | Notes |
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|--------|-------------|-------|
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| `gcd` | gcd | smoketest |
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| `aes` | aes_cipher_top | medium |
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| `ibex` | ibex_core | RISC-V core |
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| `jpeg` | jpeg_encoder | JPEG encoder |
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| `riscv32i` | riscv | RISC-V RV32I |
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| `chameleon` | soc_core | SoC with macros |
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| `microwatt` | microwatt | POWER ISA core |
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### nangate45 (7 designs)
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| Design | DESIGN_NAME | Notes |
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|--------|-------------|-------|
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| `gcd` | gcd | smoketest |
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| `aes` | aes_cipher_top | medium |
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| `ibex` | ibex_core | RISC-V core |
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| `jpeg` | jpeg_encoder | JPEG encoder |
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| `dynamic_node` | dynamic_node_top_wrap | NoC router |
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| `swerv` | swerv | SweRV EH1 |
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| `tinyRocket` | RocketTile | RISC-V Rocket |
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### gf180 (5 designs)
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| Design | DESIGN_NAME | Notes |
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|--------|-------------|-------|
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| `aes` | aes_cipher_top | medium |
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| `aes-hybrid` | aes_cipher_top | hybrid variant |
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| `ibex` | ibex_core | RISC-V core |
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| `jpeg` | jpeg_encoder | JPEG encoder |
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| `riscv32i` | riscv | RISC-V RV32I |
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### ihp-sg13g2 (6 designs)
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| Design | DESIGN_NAME | Notes |
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|--------|-------------|-------|
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| `gcd` | gcd | smoketest |
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| `aes` | aes_cipher_top | medium |
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| `ibex` | ibex_core | RISC-V core |
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| `jpeg` | jpeg_encoder | JPEG encoder |
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| `riscv32i` | riscv | RISC-V RV32I |
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| `spi` | spi | SPI controller |
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### sky130hs (5 designs)
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| Design | DESIGN_NAME | Notes |
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|--------|-------------|-------|
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| `gcd` | gcd | smoketest |
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| `aes` | aes_cipher_top | medium |
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| `ibex` | ibex_core | RISC-V core |
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| `jpeg` | jpeg_encoder | JPEG encoder |
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| `riscv32i` | riscv | RISC-V RV32I |
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## Designs Blocked on bazel-orfs Changes
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These designs have BUILD.bazel with a commented-out `orfs_design()`
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and a `TODO(bazel-orfs)` note. They need changes in bazel-orfs before
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they can be enabled.
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### Hierarchical sub-design targets (riscv32i-mock-sram)
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`asap7/riscv32i-mock-sram` uses `include designs/asap7/riscv32i/config.mk`
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in its config.mk and has a `fakeram7_256x32/` sub-design directory.
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The `orfs_designs` rule generates spurious `riscv_top_*` targets in
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the sub-design package from the parent config. This causes a build
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failure because the sub-design lacks the parent's `rules-base.json`.
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**Fix**: `orfs_designs` should only generate targets from config.mk
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files that are directly in the scanned directory, not from included
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configs resolved at Make-time.
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### Specific file references in VERILOG_FILES
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Several designs list individual files in `VERILOG_FILES` from directories
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other than the design's own `src/` tree (e.g. `$(DESIGN_HOME)/src/ariane133/ariane.sv2v.v`
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or `$(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v`). The `orfs_designs`
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rule resolves `$(wildcard ...)` patterns but does not handle explicit
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file paths that use `$(DESIGN_NAME)` or `$(DESIGN_NICKNAME)`.
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**Affected**: nangate45: ariane133, ariane136, black_parrot, bp_be_top,
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bp_fe_top, bp_multi_top, bp_quad, mempool_group, swerv_wrapper.
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**Fix**: Extend the `orfs_designs` config.mk parser to resolve
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`$(DESIGN_NAME)` and `$(DESIGN_NICKNAME)` variable references in
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explicit file paths, not just in `$(wildcard ...)` patterns.
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### VERILOG_FILES from non-matching src directory
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`gf180/uart-blocks` references `src/uart-no-param/*.v` -- a different
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src directory than its own name.
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These designs have `orfs_design()` enabled and pass `bazelisk query`:
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**Fix**: The parser already handles `$(DESIGN_NICKNAME)` in wildcard
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patterns; verify it also resolves when the source directory name
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differs from the design directory name.
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### asap7
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### Platform-local verilog in VERILOG_FILES
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- `gcd` -- smoketest, builds in ~1 minute
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- `gcd-ccs` -- gcd with CCS lib model
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- `aes` (aes_cipher_top) -- medium design
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- `aes-block` -- aes as a block
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- `aes-mbff` -- aes with MBFF
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- `aes_lvt` -- aes with LVT cells
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- `ethmac` -- Ethernet MAC
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- `ethmac_lvt` -- ethmac with LVT cells
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`ihp-sg13g2/i2c-gpio-expander` adds `$(PLATFORM_DIR)/verilog/sg13g2_io.v`
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to VERILOG_FILES and also references verilog from its own platform
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design directory (`$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/*.v`).
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### sky130hd
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**Fix**: Support `$(PLATFORM_DIR)/...` file references in VERILOG_FILES
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by resolving them against the PDK target.
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- `gcd` -- smoketest
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- `aes` (aes_cipher_top) -- medium design
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### Generated verilog (mock-alu)
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## Designs Not Yet Working
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`asap7/mock-alu` generates its verilog via `src/mock-alu/generate_*.py`
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scripts. Needs a Bazel `genrule` to run the Python generator before
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synthesis.
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Each design directory has a `BUILD.bazel` with a commented-out
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`orfs_design()` call and a note explaining what's missing. The common
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blockers are:
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### No VERILOG_FILES (minimal)
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**Missing `src/` BUILD.bazel**: The source directory (e.g.
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`flow/designs/src/jpeg/`) needs a `BUILD.bazel` with a `:verilog`
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filegroup and `exports_files`. Affected: jpeg, jpeg_lvt, uart,
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riscv32i, riscv32i-mock-sram, mock-cpu, chameleon, microwatt.
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`asap7/minimal` is a test design with no `VERILOG_FILES` in config.mk
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(empty SDC). Not expected to work with `orfs_designs`.
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**Specific file references**: Some `config.mk` files reference
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individual source files instead of wildcards. These need
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`exports_files` in the source directory. Affected: ibex,
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swerv_wrapper.
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### Platforms without public PDK
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**Complex source trees**: Designs like cva6 have deeply nested source
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trees that each need their own `BUILD.bazel`. Affected: cva6.
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**Generated verilog**: mock-alu generates its verilog via Python scripts.
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Needs a `genrule`. Affected: mock-alu.
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**No config.mk**: mock-array has no config.mk (test fixture only).
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**No verilog**: minimal is a test design with no VERILOG_FILES.
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gf12, gf55, and rapidus2hp have design directories but no platform
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files in the open-source repo. These are skipped entirely.
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## How to Add More Designs
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- **Parallel**: Independent designs build in parallel automatically.
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- **Reproducible**: Same inputs always produce the same outputs.
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## Performance Notes
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Each OpenROAD invocation uses `-threads <nproc>` (all available cores).
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When Bazel runs many designs in parallel, the machine becomes heavily
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overcommitted. On a 48-core machine, 50+ OpenROAD instances may run
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simultaneously during a full `bazelisk test ...`, each requesting 48
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threads.
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To limit parallelism:
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```bash
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# Limit to 4 concurrent OpenROAD invocations
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bazelisk test --jobs=4 ...
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```
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A full test suite run (46 designs, 6 platforms) takes roughly 3-4 hours
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on a 48-core machine with default parallelism (overcommitted). Individual
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design times vary from ~1 minute (gcd) to ~63 minutes (cva6 on asap7).
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## Updating Metric Thresholds
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When OpenROAD or flow scripts change, metric thresholds in
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submitting too many at once just causes "maintainer packet dropping"
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where reviews stall.
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Additional PDKs are throttled until asap7 and sky130hd are
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essentially clean and no longer need fix-up commits in this PR.
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## Known Limitations
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- Only asap7 and sky130hd PDKs are wired up (others can be added to
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`MODULE.bazel` platforms list and `flow/BUILD.bazel` orfs_pdk calls).
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- The Docker image is pinned; updating it requires changing
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`MODULE.bazel`.
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- Not all designs work yet (see above).
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- Platforms without public PDK files (gf12, gf55, rapidus2hp) are not
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supported.
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- Some designs are blocked on bazel-orfs parser improvements (see above).
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- `riscv32i-mock-sram` hierarchical flow does not work yet.
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- This is a beta -- expect rough edges. File issues at
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https://github.com/The-OpenROAD-Project/bazel-orfs/issues

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