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Merge branch 'master' of https://github.com/The-OpenROAD-Project-private/OpenROAD-flow-scripts into secure-grt_fill_via
2 parents 1125db7 + f5b9c3f commit ca8209a

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Lines changed: 16 additions & 2 deletions

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MODULE.bazel

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module(
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name = "orfs",
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version = "0.0.1",
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compatibility_level = 1,
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)
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bazel_dep(name = "bazel-orfs")
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remote = "https://github.com/The-OpenROAD-Project/bazel-orfs.git",
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)
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bazel_dep(name = "rules_python", version = "1.2.0")
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bazel_dep(name = "rules_python", version = "1.8.5")
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bazel_dep(name = "rules_shell", version = "0.6.1")
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python = use_extension("@rules_python//python/extensions:python.bzl", "python")
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export DESIGN_NICKNAME = riscv32i-mock-sram
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export BLOCKS=fakeram7_256x32
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# Override platform default (BLOCKS_grid_strategy.tcl) which defines an
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# ElementGrid macro grid with no stripes, producing empty PDN grids
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# (PDN-0232/0233). BLOCK_grid_strategy.tcl uses M4-M5 connections that
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# match the block's MAX_ROUTING_LAYER=M4 constraint.
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export PDN_TCL = $(PLATFORM_DIR)/openRoad/pdn/BLOCK_grid_strategy.tcl
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include designs/asap7/riscv32i/config.mk
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flow/designs/ihp-sg13g2/i2c-gpio-expander/config.mk

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export VERILOG_FILES = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/$(DESIGN_NAME).v \
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$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/I2cGpioExpander.v
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# IO pad cells -- platform config.mk adds these conditionally when
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# FOOTPRINT_TCL is set, but declare them explicitly for robustness.
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export VERILOG_FILES += $(PLATFORM_DIR)/verilog/sg13g2_io.v
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export ADDITIONAL_LEFS += $(PLATFORM_DIR)/lef/sg13g2_io.lef \
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$(PLATFORM_DIR)/lef/bondpad_70x70.lef
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export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
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export ADDITIONAL_SLOW_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_slow_1p08V_3p0V_125C.lib
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export ADDITIONAL_FAST_LIBS += $(PLATFORM_DIR)/lib/sg13g2_io_fast_1p32V_3p6V_m40C.lib
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export ADDITIONAL_GDS += $(PLATFORM_DIR)/gds/sg13g2_io.gds
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export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
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export SEAL_GDS = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/sealring.gds.gz

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