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Merge pull request #4117 from oharboe/eqy-retirement
Remove EQUIVALENCE_CHECK, superseded by LEC_CHECK
2 parents b1cf5e6 + 9fc2b77 commit e3ff72f

13 files changed

Lines changed: 1 addition & 109 deletions

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‎docs/user/FlowVariables.md‎

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@@ -137,7 +137,6 @@ configuration file.
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| <a name="DPO_MAX_DISPLACEMENT"></a>DPO_MAX_DISPLACEMENT| Specifies how far an instance can be moved when optimizing.| 5 1|
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| <a name="EARLY_SIZING_CAP_RATIO"></a>EARLY_SIZING_CAP_RATIO| Ratio between the input pin capacitance and the output pin load during initial gate sizing.| |
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| <a name="ENABLE_DPO"></a>ENABLE_DPO| Enable detail placement with improve_placement feature.| 1|
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| <a name="EQUIVALENCE_CHECK"></a>EQUIVALENCE_CHECK| Enable running equivalence checks to verify logical correctness of repair_timing.| 0|
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| <a name="FASTROUTE_TCL"></a>FASTROUTE_TCL| Specifies a Tcl script with commands to run before FastRoute.| |
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| <a name="FILL_CELLS"></a>FILL_CELLS| Fill cells are used to fill empty sites. If not set or empty, fill cell insertion is skipped.| |
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| <a name="FILL_CONFIG"></a>FILL_CONFIG| JSON rule file for metal fill during chip finishing.| |
@@ -230,7 +229,6 @@ configuration file.
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| <a name="RCX_RULES"></a>RCX_RULES| RC Extraction rules file path.| |
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| <a name="RECOVER_POWER"></a>RECOVER_POWER| Specifies how many percent of paths with positive slacks can be slowed for power savings [0-100].| 0|
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| <a name="REMOVE_ABC_BUFFERS"></a>REMOVE_ABC_BUFFERS (deprecated)| Remove abc buffers from the netlist. If timing repair in floorplanning is taking too long, use a SETUP/HOLD_SLACK_MARGIN to terminate timing repair early instead of using REMOVE_ABC_BUFFERS or set SKIP_LAST_GASP=1.| 0|
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| <a name="REMOVE_CELLS_FOR_EQY"></a>REMOVE_CELLS_FOR_EQY| String patterns directly passed to write_verilog -remove_cells <> for equivalence checks.| |
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| <a name="REMOVE_CELLS_FOR_LEC"></a>REMOVE_CELLS_FOR_LEC| String patterns directly passed to write_verilog -remove_cells <> for lec checks.| |
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| <a name="REPAIR_PDN_VIA_LAYER"></a>REPAIR_PDN_VIA_LAYER| Remove power grid vias which generate DRC violations after detailed routing.| |
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| <a name="REPORT_CLOCK_SKEW"></a>REPORT_CLOCK_SKEW| Report clock skew as part of reporting metrics, starting at CTS, before which there is no clock skew. This metric can be quite time-consuming, so it can be useful to disable.| 1|
@@ -480,14 +478,12 @@ configuration file.
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- [CTS_SNAPSHOT](#CTS_SNAPSHOT)
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- [CTS_SNAPSHOTS](#CTS_SNAPSHOTS)
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- [DETAILED_METRICS](#DETAILED_METRICS)
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- [EQUIVALENCE_CHECK](#EQUIVALENCE_CHECK)
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- [HOLD_SLACK_MARGIN](#HOLD_SLACK_MARGIN)
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- [LEC_CHECK](#LEC_CHECK)
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- [MATCH_CELL_FOOTPRINT](#MATCH_CELL_FOOTPRINT)
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- [MAX_REPAIR_TIMING_ITER](#MAX_REPAIR_TIMING_ITER)
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- [POST_CTS_TCL](#POST_CTS_TCL)
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- [PRE_CTS_TCL](#PRE_CTS_TCL)
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- [REMOVE_CELLS_FOR_EQY](#REMOVE_CELLS_FOR_EQY)
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- [REPORT_CLOCK_SKEW](#REPORT_CLOCK_SKEW)
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- [SETUP_REPAIR_SEQUENCE](#SETUP_REPAIR_SEQUENCE)
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- [SETUP_SLACK_MARGIN](#SETUP_SLACK_MARGIN)

‎flow/designs/asap7/aes/config.mk‎

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@@ -13,16 +13,13 @@ export CORE_ASPECT_RATIO = 1
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export CORE_MARGIN = 2
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export PLACE_DENSITY = 0.65
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export TNS_END_PERCENT = 100
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export EQUIVALENCE_CHECK ?= 1
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export REMOVE_CELLS_FOR_EQY = TAPCELL*
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ifeq ($(FLOW_VARIANT),top)
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export DESIGN_NAME = aes_cipher_top
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export SYNTH_BLACKBOXES = aes_key_expand_128
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else ifeq ($(FLOW_VARIANT),blackbox)
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export DESIGN_NAME = aes_key_expand_128
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else ifeq ($(FLOW_VARIANT),combine)
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export EQUIVALENCE_CHECK = 0
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# List blackbox twice to demonstrates that duplicate modules are ignored.
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export SYNTH_NETLIST_FILES = \
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$(WORK_HOME)/results/$(PLATFORM)/$(DESIGN_NICKNAME)/top/1_synth.v \

‎flow/designs/asap7/jpeg/config.mk‎

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@@ -14,7 +14,4 @@ export CORE_MARGIN = 2
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export PLACE_DENSITY = 0.75
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export TNS_END_PERCENT = 100
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export EQUIVALENCE_CHECK ?= 1
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export REMOVE_CELLS_FOR_EQY = TAPCELL*
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2017

‎flow/designs/asap7/uart/config.mk‎

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@@ -13,8 +13,6 @@ export PLACE_DENSITY = 0.70
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export DIE_AREA = 0 0 17 17
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export CORE_AREA = 1.08 1.08 16 16
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export TNS_END_PERCENT = 100
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export EQUIVALENCE_CHECK ?= 1
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export REMOVE_CELLS_FOR_EQY = TAPCELL*
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export SKIP_GATE_CLONING = 1
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export VERILOG_TOP_PARAMS = DATA_WIDTH 8
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export SYNTH_HDL_FRONTEND = slang

‎flow/designs/nangate45/aes/config.mk‎

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@@ -9,8 +9,6 @@ export FLOORPLAN_DEF = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/aes_ng45_fp
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export PLACE_DENSITY_LB_ADDON = 0.20
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export TNS_END_PERCENT = 100
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export REMOVE_CELLS_FOR_EQY = TAPCELL*
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# workaround for high congestion in post-grt repair
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export SKIP_INCREMENTAL_REPAIR = 1
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‎flow/designs/nangate45/gcd/config.mk‎

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@@ -11,7 +11,6 @@ export ADDER_MAP_FILE :=
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export CORE_UTILIZATION ?= 55
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export PLACE_DENSITY_LB_ADDON = 0.20
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export TNS_END_PERCENT = 100
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export REMOVE_CELLS_FOR_EQY = TAPCELL*
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export SYNTH_REPEATABLE_BUILD ?= 1
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# This needs a smaller pitch to accomodate a small block

‎flow/designs/sky130hd/gcd/config.mk‎

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@@ -9,8 +9,5 @@ export ADDER_MAP_FILE :=
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export CORE_UTILIZATION = 40
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export TNS_END_PERCENT = 100
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export EQUIVALENCE_CHECK ?= 1
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export REMOVE_CELLS_FOR_EQY = sky130_fd_sc_hd__tapvpwrvgnd*
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export SWAP_ARITH_OPERATORS = 1
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export OPENROAD_HIERARCHICAL = 1

‎flow/designs/sky130hs/gcd/config.mk‎

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@@ -11,8 +11,5 @@ export ADDER_MAP_FILE :=
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export CORE_UTILIZATION = 50
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export PLACE_DENSITY_LB_ADDON = 0.1
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export TNS_END_PERCENT = 100
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export EQUIVALENCE_CHECK ?= 1
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export REMOVE_CELLS_FOR_EQY = sky130_fd_sc_hs__tapvpwrvgnd*
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#export SYNTH_HDL_FRONTEND ?= slang
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#export OPENROAD_HIERARCHICAL ?= 1

‎flow/scripts/cts.tcl‎

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@@ -59,18 +59,12 @@ if { $::env(CTS_SNAPSHOTS) } {
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}
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if { !$::env(SKIP_CTS_REPAIR_TIMING) } {
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if { $::env(EQUIVALENCE_CHECK) } {
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write_eqy_verilog 4_before_rsz.v
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}
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if { $::env(LEC_CHECK) } {
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write_lec_verilog 4_before_rsz_lec.v
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}
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repair_timing_helper
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if { $::env(EQUIVALENCE_CHECK) } {
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run_equivalence_test
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}
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if { $::env(LEC_CHECK) } {
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write_lec_verilog 4_after_rsz_lec.v
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run_lec_test 4_rsz 4_before_rsz_lec.v 4_after_rsz_lec.v

‎flow/scripts/load.tcl‎

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@@ -49,70 +49,3 @@ proc load_design { design_file sdc_file } {
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set_delay_calculator prima
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}
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}
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#===========================================================================================
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# Routines to run equivalence tests when they are enabled.
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proc write_eqy_verilog { filename } {
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# Filter out cells with no verilog/not needed for equivalence such
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# as fillers and tap cells
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if { [env_var_exists_and_non_empty REMOVE_CELLS_FOR_EQY] } {
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write_verilog -remove_cells $::env(REMOVE_CELLS_FOR_EQY) $::env(RESULTS_DIR)/$filename
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} else {
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write_verilog $::env(RESULTS_DIR)/$filename
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}
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}
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proc write_eqy_script { } {
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set top_cell [current_design]
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set outfile [open "$::env(OBJECTS_DIR)/4_eqy_test.eqy" w]
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# Gold netlist
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puts $outfile "\[gold]\nread_liberty -ignore_miss_func $::env(LIB_FILES)\n"
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puts $outfile "read_verilog -sv $::env(RESULTS_DIR)/4_before_rsz.v\n"
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puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
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# Modified netlist
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puts $outfile "\[gate]\nread_liberty -ignore_miss_func $::env(LIB_FILES)\n"
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puts $outfile "read_verilog -sv $::env(RESULTS_DIR)/4_after_rsz.v\n"
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puts $outfile "prep -top $top_cell -flatten\nmemory_map\n\n"
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# Recommendation from eqy team on how to speed up a design
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puts $outfile "\[match *]\ngate-nomatch _*_.*"
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# See issue OpenROAD#6545 "Equivalence check failure due to non-unique resizer nets"
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puts $outfile "gate-nomatch net*"
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# Forbid matching on buffer instances or cloned instances to make it less
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# likely EQY will fail to prove equivalence because of its assuming structural
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# similarity between gold and gate netlists. This doesn't remove coverage.
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puts $outfile "gate-nomatch clone*"
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puts $outfile "gate-nomatch place*"
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puts $outfile "gate-nomatch rebuffer*"
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puts $outfile "gate-nomatch wire*"
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puts $outfile "gate-nomatch place*\n\n"
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# Equivalence check recipe 1
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puts $outfile "\[strategy basic]\nuse sat\ndepth 10\n\n"
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# Equivalence check recipe 2
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puts $outfile "\[strategy sby]\nuse sby\ndepth 10\nengine smtbmc bitwuzla\n\n"
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close $outfile
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}
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proc run_equivalence_test { } {
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write_eqy_verilog 4_after_rsz.v
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write_eqy_script
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# tclint-disable-next-line command-args
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eval exec eqy -d $::env(LOG_DIR)/4_eqy_output \
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--force \
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--jobs $::env(NUM_CORES) \
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$::env(OBJECTS_DIR)/4_eqy_test.eqy \
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> $::env(LOG_DIR)/4_equivalence_check.log
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set count \
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[exec grep -c "Successfully proved designs equivalent" $::env(LOG_DIR)/4_equivalence_check.log]
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if { $count == 0 } {
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error "Repair timing output failed equivalence test"
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} else {
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puts "Repair timing output passed equivalence test"
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}
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}

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