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#define _CRT_SECURE_NO_WARNINGS
#include <inttypes.h>
#include <stdio.h>
#include <string.h>
#include <sstream>
#include "binaryninjaapi.h"
#include "il.h"
extern "C" {
#include "xed-interface.h"
}
#include "arch_x86_common_architecture.h"
using namespace BinaryNinja;
using namespace std;
enum Elfx86RelocationType : uint32_t
{
R_386_NONE = 0, // No relocation.
R_386_32 = 1, // Add symbol value.
R_386_PC32 = 2, // Add PC-relative symbol value.
R_386_GOT32 = 3, // Add PC-relative GOT offset.
R_386_PLT32 = 4, // Add PC-relative PLT offset.
R_386_COPY = 5, // Copy data from shared object.
R_386_GLOB_DAT = 6, // Set GOT entry to data address.
R_386_JUMP_SLOT = 7, // Set GOT entry to code address.
R_386_RELATIVE = 8, // Add load address of shared object.
R_386_GOTOFF = 9, // Add GOT-relative symbol address.
R_386_GOTPC = 10, // Add PC-relative GOT table address.
R_386_TLS_TPOFF = 14, // Negative offset in static TLS block
R_386_TLS_IE = 15, // Absolute address of GOT for -ve static TLS
R_386_TLS_GOTIE = 16, // GOT entry for negative static TLS block
R_386_TLS_LE = 17, // Negative offset relative to static TLS
R_386_TLS_GD = 18, // 32 bit offset to GOT (index,off) pair
R_386_TLS_LDM = 19, // 32 bit offset to GOT (index,zero) pair
R_386_16 = 20, //
R_386_PC16 = 21, //
R_386_8 = 22, //
R_386_PC8 = 23, //
R_386_TLS_GD_32 = 24, // 32 bit offset to GOT (index,off) pair
R_386_TLS_GD_PUSH = 25, // pushl instruction for Sun ABI GD sequence
R_386_TLS_GD_CALL = 26, // call instruction for Sun ABI GD sequence
R_386_TLS_GD_POP = 27, // popl instruction for Sun ABI GD sequence
R_386_TLS_LDM_32 = 28, // 32 bit offset to GOT (index,zero) pair
R_386_TLS_LDM_PUSH = 29, // pushl instruction for Sun ABI LD sequence
R_386_TLS_LDM_CALL = 30, // call instruction for Sun ABI LD sequence
R_386_TLS_LDM_POP = 31, // popl instruction for Sun ABI LD sequence
R_386_TLS_LDO_32 = 32, // 32 bit offset from start of TLS block
R_386_TLS_IE_32 = 33, // 32 bit offset to GOT static TLS offset entry
R_386_TLS_LE_32 = 34, // 32 bit offset within static TLS block
R_386_TLS_DTPMOD32 = 35, // GOT entry containing TLS index
R_386_TLS_DTPOFF32 = 36, // GOT entry containing TLS offset
R_386_TLS_TPOFF32 = 37, // GOT entry of -ve static TLS offset
R_386_SIZE32 = 38, //
R_386_TLS_GOTDESC = 39, //
R_386_TLS_DESC_CALL = 40, //
R_386_TLS_DESC = 41, //
R_386_IRELATIVE = 42, // PLT entry resolved indirectly at runtime
MAX_ELF_X86_RELOCATION
};
enum Elfx64RelocationType : uint32_t
{
R_X86_64_NONE = 0, // No reloc
R_X86_64_64 = 1, // Direct 64 bit
R_X86_64_PC32 = 2, // PC relative 32 bit signed
R_X86_64_GOT32 = 3, // 32 bit GOT entry
R_X86_64_PLT32 = 4, // 32 bit PLT address
R_X86_64_COPY = 5, // Copy symbol at runtime
R_X86_64_GLOB_DAT = 6, // Create GOT entry
R_X86_64_JUMP_SLOT = 7, // Create PLT entry
R_X86_64_RELATIVE = 8, // Adjust by program base
R_X86_64_GOTPCREL = 9, // 32 bit signed pc relative offset to GOT
R_X86_64_32 = 10, // Direct 32 bit zero extended
R_X86_64_32S = 11, // Direct 32 bit sign extended
R_X86_64_16 = 12, // Direct 16 bit zero extended
R_X86_64_PC16 = 13, // 16 bit sign extended pc relative
R_X86_64_8 = 14, // Direct 8 bit sign extended
R_X86_64_PC8 = 15, // 8 bit sign extended pc relative
R_X86_64_DTPMOD64 = 16,
R_X86_64_DTPOFF64 = 17,
R_X86_64_TPOFF64 = 18,
R_X86_64_TLSGD = 19,
R_X86_64_TLSLD = 20,
R_X86_64_DTPOFF32 = 21,
R_X86_64_GOTTPOFF = 22,
R_X86_64_TPOFF32 = 23,
R_X86_64_PC64 = 24,
R_X86_64_GOTOFF64 = 25,
R_X86_64_GOTPC32 = 26,
R_X86_64_GOT64 = 27,
R_X86_64_GOTPCREL64 = 28,
R_X86_64_GOTPC64 = 29,
R_X86_64_GOTPLT64 = 30,
R_X86_64_PLTOFF64 = 31,
R_X86_64_SIZE32 = 32,
R_X86_64_SIZE64 = 33,
R_X86_64_GOTPC32_TLSDESC = 34,
R_X86_64_TLSDESC_CALL = 35,
R_X86_64_TLSDESC = 36,
R_X86_64_IRELATIVE = 37,
R_X86_64_RELATIVE64 = 38,
R_X86_64_PC32_BND = 39,
R_X86_64_PLT32_BND = 40,
R_X86_64_GOTPCRELX = 41,
R_X86_64_REX_GOTPCRELX = 42,
MAX_ELF_X64_RELOCATION
};
enum Machox86RelocationType : uint32_t
{
GENERIC_RELOC_VANILLA = 0,
GENERIC_RELOC_PAIR = 1,
GENERIC_RELOC_SECTDIFF = 2,
GENERIC_RELOC_PB_LA_PTR = 3,
GENERIC_RELOC_LOCAL_SECTDIFF = 4,
GENERIC_RELOC_TLV = 5,
MACHO_MAX_X86_RELOCATION
};
enum Machox64RelocationType : uint32_t
{
X86_64_RELOC_UNSIGNED = 0,
X86_64_RELOC_SIGNED = 1,
X86_64_RELOC_BRANCH = 2,
X86_64_RELOC_GOT_LOAD = 3,
X86_64_RELOC_GOT = 4,
X86_64_RELOC_SUBTRACTOR = 5,
X86_64_RELOC_SIGNED_1 = 6,
X86_64_RELOC_SIGNED_2 = 7,
X86_64_RELOC_SIGNED_4 = 8,
X86_64_RELOC_TLV = 9,
MACHO_MAX_X86_64_RELOCATION
};
enum COFFx86RelocationType : uint32_t
{
PE_IMAGE_REL_I386_ABSOLUTE = 0x0000, // The relocation is ignored.
PE_IMAGE_REL_I386_DIR16 = 0x0001, // Not supported.
PE_IMAGE_REL_I386_REL16 = 0x0002, // Not supported.
PE_IMAGE_REL_I386_DIR32 = 0x0006, // The target's 32-bit VA.
PE_IMAGE_REL_I386_DIR32NB = 0x0007, // The target's 32-bit RVA.
PE_IMAGE_REL_I386_SEG12 = 0x0009, // Not supported.
PE_IMAGE_REL_I386_SECTION = 0x000A, // The 16-bit section index of the section that contains the target. This is used to support debugging information.
PE_IMAGE_REL_I386_SECREL = 0x000B, // The 32-bit offset of the target from the beginning of its section. This is used to support debugging information and static thread local storage.
PE_IMAGE_REL_I386_TOKEN = 0x000C, // The CLR token.
PE_IMAGE_REL_I386_SECREL7 = 0x000D, // A 7-bit offset from the base of the section that contains the target.
PE_IMAGE_REL_I386_REL32 = 0x0014, // The 32-bit relative displacement to the target. This supports the x86 relative branch and call instructions.
MAX_PE_X86_RELOCATION
};
enum COFFx64RelocationType : uint32_t
{
PE_IMAGE_REL_AMD64_ABSOLUTE = 0x0000, // The relocation is ignored.
PE_IMAGE_REL_AMD64_ADDR64 = 0x0001, // The 64-bit VA of the relocation target.
PE_IMAGE_REL_AMD64_ADDR32 = 0x0002, // The 32-bit VA of the relocation target.
PE_IMAGE_REL_AMD64_ADDR32NB = 0x0003, // The 32-bit address without an image base (RVA).
PE_IMAGE_REL_AMD64_REL32 = 0x0004, // The 32-bit relative address from the byte following the relocation.
PE_IMAGE_REL_AMD64_REL32_1 = 0x0005, // The 32-bit address relative to byte distance 1 from the relocation.
PE_IMAGE_REL_AMD64_REL32_2 = 0x0006, // The 32-bit address relative to byte distance 2 from the relocation.
PE_IMAGE_REL_AMD64_REL32_3 = 0x0007, // The 32-bit address relative to byte distance 3 from the relocation.
PE_IMAGE_REL_AMD64_REL32_4 = 0x0008, // The 32-bit address relative to byte distance 4 from the relocation.
PE_IMAGE_REL_AMD64_REL32_5 = 0x0009, // The 32-bit address relative to byte distance 5 from the relocation.
PE_IMAGE_REL_AMD64_SECTION = 0x000A, // The 16-bit section index of the section that contains the target. This is used to support debugging information.
PE_IMAGE_REL_AMD64_SECREL = 0x000B, // The 32-bit offset of the target from the beginning of its section. This is used to support debugging information and static thread local storage.
PE_IMAGE_REL_AMD64_SECREL7 = 0x000C, // A 7-bit unsigned offset from the base of the section that contains the target.
PE_IMAGE_REL_AMD64_TOKEN = 0x000D, // CLR tokens.
PE_IMAGE_REL_AMD64_SREL32 = 0x000E, // A 32-bit signed span-dependent value emitted into the object.
PE_IMAGE_REL_AMD64_PAIR = 0x000F, // A pair that must immediately follow every span-dependent value.
PE_IMAGE_REL_AMD64_SSPAN32 = 0x0010, // A 32-bit signed span-dependent value that is applied at link time.
MAX_PE_X64_RELOCATION
};
enum PeRelocationType : uint32_t
{
PE_IMAGE_USER_DEFINED = 0xffffffff, // User defined relocation type for synthesized relocations at IAT sites.
PE_IMAGE_REL_BASED_ABSOLUTE = 0, // The base relocation is skipped. This type can be used to pad a block.
PE_IMAGE_REL_BASED_HIGH = 1, // The base relocation adds the high 16 bits of the difference to the 16-bit field at offset. The 16-bit field represents the high value of a 32-bit word.
PE_IMAGE_REL_BASED_LOW = 2, // The base relocation adds the low 16 bits of the difference to the 16-bit field at offset. The 16-bit field represents the low half of a 32-bit word.
PE_IMAGE_REL_BASED_HIGHLOW = 3, // The base relocation applies all 32 bits of the difference to the 32-bit field at offset.
PE_IMAGE_REL_BASED_HIGHADJ = 4, // The base relocation adds the high 16 bits of the difference to the 16-bit field at offset. The 16-bit field represents the high value of a 32-bit word. The low 16 bits of the 32-bit value are stored in the 16-bit word that follows this base relocation. This means that this base relocation occupies two slots.
PE_IMAGE_REL_BASED_MIPS_JMPADDR = 5, // The relocation interpretation is dependent on the machine type. When the machine type is MIPS, the base relocation applies to a MIPS jump instruction.
PE_IMAGE_REL_BASED_ARM_MOV32 = 5, // This relocation is meaningful only when the machine type is ARM or Thumb. The base relocation applies the 32-bit address of a symbol across a consecutive MOVW/MOVT instruction pair.
PE_IMAGE_REL_BASED_RISCV_HIGH20 = 5, // This relocation is only meaningful when the machine type is RISC-V. The base relocation applies to the high 20 bits of a 32-bit absolute address.
PE_IMAGE_REL_BASE_RESERVED = 6, // Reserved, must be zero.
PE_IMAGE_REL_BASED_THUMB_MOV32 = 7, // This relocation is meaningful only when the machine type is Thumb. The base relocation applies the 32-bit address of a symbol to a consecutive MOVW/MOVT instruction pair.
PE_IMAGE_REL_BASED_RISCV_LOW12I = 7, // This relocation is only meaningful when the machine type is RISC-V. The base relocation applies to the low 12 bits of a 32-bit absolute address formed in RISC-V I-type instruction format.
PE_IMAGE_REL_BASED_RISCV_LOW12S = 8, // This relocation is only meaningful when the machine type is RISC-V. The base relocation applies to the low 12 bits of a 32-bit absolute address formed in RISC-V S-type instruction format.
PE_IMAGE_REL_BASED_MIPS_JMPADDR16 = 9, // The relocation is only meaningful when the machine type is MIPS. The base relocation applies to a MIPS16 jump instruction.
PE_IMAGE_REL_BASED_DIR64 = 10, // The base relocation applies the difference to the 64-bit field at offset.
MAX_PE_RELOCATION
};
static const char* GetRelocationString(PeRelocationType relocType)
{
static const char* relocTable[] =
{
"PE_IMAGE_REL_BASED_ABSOLUTE",
"PE_IMAGE_REL_BASED_HIGH",
"PE_IMAGE_REL_BASED_LOW",
"PE_IMAGE_REL_BASED_HIGHLOW",
"PE_IMAGE_REL_BASED_HIGHADJ",
"PE_IMAGE_REL_BASED_MIPS_JMPADDR",
"PE_IMAGE_REL_BASED_ARM_MOV32",
"PE_IMAGE_REL_BASED_RISCV_HIGH20",
"PE_IMAGE_REL_BASE_RESERVED",
"PE_IMAGE_REL_BASED_THUMB_MOV32",
"PE_IMAGE_REL_BASED_RISCV_LOW12I",
"PE_IMAGE_REL_BASED_RISCV_LOW12S",
"PE_IMAGE_REL_BASED_MIPS_JMPADDR16",
"PE_IMAGE_REL_BASED_DIR64"
};
if (relocType < MAX_PE_RELOCATION)
return relocTable[relocType];
return "Unknown relocation";
}
static const char* GetRelocationString(COFFx86RelocationType relocType)
{
static const char* relocTable[] =
{
"PE_IMAGE_REL_I386_ABSOLUTE",
"PE_IMAGE_REL_I386_DIR16",
"PE_IMAGE_REL_I386_REL16",
"", "", "",
"PE_IMAGE_REL_I386_DIR32",
"PE_IMAGE_REL_I386_DIR32NB",
"",
"PE_IMAGE_REL_I386_SEG12",
"PE_IMAGE_REL_I386_SECTION",
"PE_IMAGE_REL_I386_SECREL",
"PE_IMAGE_REL_I386_TOKEN",
"PE_IMAGE_REL_I386_SECREL7",
"", "", "", "", "", "",
"PE_IMAGE_REL_I386_REL32",
};
if (relocType < MAX_PE_X86_RELOCATION)
return relocTable[relocType];
return "Unknown x86 relocation";
}
static const char* GetRelocationString(COFFx64RelocationType relocType)
{
static const char* relocTable[] =
{
"PE_IMAGE_REL_AMD64_ABSOLUTE",
"PE_IMAGE_REL_AMD64_ADDR64",
"PE_IMAGE_REL_AMD64_ADDR32",
"PE_IMAGE_REL_AMD64_ADDR32NB",
"PE_IMAGE_REL_AMD64_REL32",
"PE_IMAGE_REL_AMD64_REL32_1",
"PE_IMAGE_REL_AMD64_REL32_2",
"PE_IMAGE_REL_AMD64_REL32_3",
"PE_IMAGE_REL_AMD64_REL32_4",
"PE_IMAGE_REL_AMD64_REL32_5",
"PE_IMAGE_REL_AMD64_SECTION",
"PE_IMAGE_REL_AMD64_SECREL",
"PE_IMAGE_REL_AMD64_SECREL7",
"PE_IMAGE_REL_AMD64_TOKEN",
"PE_IMAGE_REL_AMD64_SREL32",
"PE_IMAGE_REL_AMD64_PAIR",
"PE_IMAGE_REL_AMD64_SSPAN32",
};
if (relocType < MAX_PE_X64_RELOCATION)
return relocTable[relocType];
return "Unknown x86_64 relocation";
}
static const char* GetRelocationString(Elfx86RelocationType relocType)
{
static const char* relocTable[] =
{
"R_386_NONE",
"R_386_32",
"R_386_PC32",
"R_386_GOT32",
"R_386_PLT32",
"R_386_COPY",
"R_386_GLOB_DAT",
"R_386_JUMP_SLOT",
"R_386_RELATIVE",
"R_386_GOTOFF",
"R_386_GOTPC",
"",
"",
"",
"R_386_TLS_TPOFF",
"R_386_TLS_IE",
"R_386_TLS_GOTIE",
"R_386_TLS_LE",
"R_386_TLS_GD",
"R_386_TLS_LDM",
"R_386_16",
"R_386_PC16",
"R_386_8",
"R_386_PC8",
"R_386_TLS_GD_32",
"R_386_TLS_GD_PUSH",
"R_386_TLS_GD_CALL",
"R_386_TLS_GD_POP",
"R_386_TLS_LDM_32",
"R_386_TLS_LDM_PUSH",
"R_386_TLS_LDM_CALL",
"R_386_TLS_LDM_POP",
"R_386_TLS_LDO_32",
"R_386_TLS_IE_32",
"R_386_TLS_LE_32",
"R_386_TLS_DTPMOD32",
"R_386_TLS_DTPOFF32",
"R_386_TLS_TPOFF32",
"R_386_SIZE32",
"R_386_TLS_GOTDESC",
"R_386_TLS_DESC_CALL",
"R_386_TLS_DESC",
"R_386_IRELATIVE",
};
if (relocType < MAX_ELF_X86_RELOCATION)
return relocTable[relocType];
return "Unknown x86 relocation";
}
static const char* GetRelocationString(Elfx64RelocationType relocType)
{
static const char* relocTable[] = {
"R_X86_64_NONE",
"R_X86_64_64",
"R_X86_64_PC32",
"R_X86_64_GOT32",
"R_X86_64_PLT32",
"R_X86_64_COPY",
"R_X86_64_GLOB_DAT",
"R_X86_64_JUMP_SLOT",
"R_X86_64_RELATIVE",
"R_X86_64_GOTPCREL",
"R_X86_64_32",
"R_X86_64_32S",
"R_X86_64_16",
"R_X86_64_PC16",
"R_X86_64_8",
"R_X86_64_PC8",
"R_X86_64_DTPMOD64",
"R_X86_64_DTPOFF64",
"R_X86_64_TPOFF64",
"R_X86_64_TLSGD",
"R_X86_64_TLSLD",
"R_X86_64_DTPOFF32",
"R_X86_64_GOTTPOFF",
"R_X86_64_TPOFF32",
"R_X86_64_PC64",
"R_X86_64_GOTOFF64",
"R_X86_64_GOTPC32",
"R_X86_64_GOT64",
"R_X86_64_GOTPCREL64",
"R_X86_64_GOTPC64",
"R_X86_64_GOTPLT64",
"R_X86_64_PLTOFF64",
"R_X86_64_SIZE32",
"R_X86_64_SIZE64",
"R_X86_64_GOTPC32_TLSDESC",
"R_X86_64_TLSDESC_CALL",
"R_X86_64_TLSDESC",
"R_X86_64_IRELATIVE",
"R_X86_64_RELATIVE64",
"R_X86_64_PC32_BND",
"R_X86_64_PLT32_BND",
"R_X86_64_GOTPCRELX",
"R_X86_64_REX_GOTPCRELX"};
if (relocType < MAX_ELF_X64_RELOCATION)
return relocTable[relocType];
return "Unknown x86_64 relocation";
}
static const char* GetRelocationString(Machox86RelocationType relocType)
{
static const char* relocTable[] = {
"GENERIC_RELOC_VANILLA",
"GENERIC_RELOC_PAIR",
"GENERIC_RELOC_SECTDIFF",
"GENERIC_RELOC_PB_LA_PTR",
"GENERIC_RELOC_LOCAL_SECTDIFF",
"GENERIC_RELOC_TLV",
};
if (relocType < MACHO_MAX_X86_RELOCATION)
return relocTable[relocType];
return "Unknown x86 relocation";
}
static const char* GetRelocationString(Machox64RelocationType relocType)
{
static const char* relocTable[] = {
"X86_64_RELOC_UNSIGNED",
"X86_64_RELOC_SIGNED",
"X86_64_RELOC_BRANCH",
"X86_64_RELOC_GOT_LOAD",
"X86_64_RELOC_GOT",
"X86_64_RELOC_SUBTRACTOR",
"X86_64_RELOC_SIGNED_1",
"X86_64_RELOC_SIGNED_2",
"X86_64_RELOC_SIGNED_4",
"X86_64_RELOC_TLV"
};
if (relocType < MACHO_MAX_X86_64_RELOCATION)
return relocTable[relocType];
return "Unknown x64 relocation";
}
bool X86CommonArchitecture::Decode(const uint8_t* data, size_t len, xed_decoded_inst_t* xedd)
{
// Zero out structure data, and keep the current destructuring mode (32/64/etc)
xed_decoded_inst_zero_keep_mode(xedd);
xed3_operand_set_cet(xedd, 1);
xed3_operand_set_mpxmode(xedd, m_disassembly_options.mpx);
// Decode the data and check for errors
xed_error_enum_t xed_error = xed_decode(xedd, data, (unsigned)len);
switch(xed_error)
{
case XED_ERROR_NONE:
return true;
default:
return false;
}
}
size_t X86CommonArchitecture::GetAddressSizeBits() const
{
return GetAddressSize() * 8;
}
uint64_t X86CommonArchitecture::GetAddressMask() const
{
if (GetAddressSizeBits() == 64)
return (uint64_t)-1;
return (((uint64_t)1) << GetAddressSizeBits()) - 1;
}
void X86CommonArchitecture::SetInstructionInfoForInstruction(uint64_t addr, InstructionInfo& result, xed_decoded_inst_t* xedd)
{
result.length = xed_decoded_inst_get_length(xedd);
const uint64_t abs_br = xed_decoded_inst_get_branch_displacement(xedd) + addr + xed_decoded_inst_get_length(xedd);
const xed_iform_enum_t xedd_iForm = xed_decoded_inst_get_iform_enum(xedd);
const xed_iclass_enum_t xedd_iClass = xed_decoded_inst_get_iclass(xedd);
const uint64_t immediateOne = xed_decoded_inst_get_unsigned_immediate(xedd);
// 1. First parse 'generally', by instruction category, then
// 2. break down to special cases and impliment iclass and possibly iform-specific cases
switch (xed_decoded_inst_get_category(xedd))
{
case XED_CATEGORY_CALL:
// CALL instruction with an immediate as the first operand and it's not the next instruction
if ((abs_br != addr+result.length) && ((xedd_iForm == XED_IFORM_CALL_NEAR_RELBRz) || (xedd_iForm == XED_IFORM_CALL_NEAR_RELBRd)))
result.AddBranch(CallDestination, abs_br);
break;
case XED_CATEGORY_UNCOND_BR:
if (xed_operand_name(xed_inst_operand(xed_decoded_inst_inst(xedd), 0)) == XED_OPERAND_RELBR)
result.AddBranch(UnconditionalBranch, abs_br);
else if (xedd_iClass != XED_ICLASS_XABORT)
result.AddBranch(UnresolvedBranch);
break;
case XED_CATEGORY_COND_BR:
result.AddBranch(TrueBranch, abs_br);
result.AddBranch(FalseBranch, addr + result.length);
break;
case XED_CATEGORY_INTERRUPT:
if (xed_decoded_inst_get_unsigned_immediate(xedd) == 0x80)
result.AddBranch(SystemCall);
else if (xedd_iClass == XED_ICLASS_INT3 || (xedd_iClass == XED_ICLASS_INT && immediateOne == 0x29))
result.AddBranch(ExceptionBranch);
break;
case XED_CATEGORY_SYSCALL:
result.AddBranch(SystemCall);
break;
case XED_CATEGORY_SYSRET:
result.AddBranch(FunctionReturn);
break;
case XED_CATEGORY_RET:
result.AddBranch(FunctionReturn);
break;
default:
switch (xedd_iClass)
{
// case XED_ICLASS_UD0:
// case XED_ICLASS_UD1:
case XED_ICLASS_UD2:
case XED_ICLASS_HLT:
result.AddBranch(ExceptionBranch);
break;
default:
break;
}
break;
}
}
bool X86CommonArchitecture::IsConditionalJump(xed_decoded_inst_t* xedd)
{
return (xed_decoded_inst_get_category(xedd) == XED_CATEGORY_COND_BR);
}
string X86CommonArchitecture::GetSizeString(const size_t size) const
{
switch (size)
{
case 1:
return "byte ";
case 2:
return "word ";
case 4:
return "dword ";
case 8:
return "qword ";
case 10:
return "tword ";
case 16:
return "oword ";
default:
return "";
}
}
BNRegisterInfo X86CommonArchitecture::RegisterInfo(xed_reg_enum_t fullWidthReg, size_t offset, size_t size, bool zeroExtend)
{
BNRegisterInfo result;
result.fullWidthRegister = fullWidthReg;
result.offset = offset;
result.size = size;
result.extend = zeroExtend ? ZeroExtendToFullWidth : NoExtend;
return result;
}
void X86CommonArchitecture::GetAddressSizeToken(const short bytes, vector<InstructionTextToken>& result, const bool lowerCase)
{
// Size
result.emplace_back(BeginMemoryOperandToken, "");
switch (bytes)
{
case 1:
if (lowerCase)
result.emplace_back(KeywordToken, "byte ");
else
result.emplace_back(KeywordToken, "BYTE ");
break;
case 2:
if (lowerCase)
result.emplace_back(KeywordToken, "word ");
else
result.emplace_back(KeywordToken, "WORD ");
break;
case 4:
if (lowerCase)
result.emplace_back(KeywordToken, "dword ");
else
result.emplace_back(KeywordToken, "DWORD ");
break;
case 8:
if (lowerCase)
result.emplace_back(KeywordToken, "qword ");
else
result.emplace_back(KeywordToken, "QWORD ");
break;
case 10:
if (lowerCase)
result.emplace_back(KeywordToken, "tword ");
else
result.emplace_back(KeywordToken, "TWORD ");
break;
case 16:
if (lowerCase)
result.emplace_back(KeywordToken, "xmmword ");
else
result.emplace_back(KeywordToken, "XMMWORD ");
break;
case 32:
if (lowerCase)
result.emplace_back(KeywordToken, "ymmword ");
else
result.emplace_back(KeywordToken, "YMMWORD ");
break;
case 64:
if (lowerCase)
result.emplace_back(KeywordToken, "zmmword ");
else
result.emplace_back(KeywordToken, "ZMMWORD ");
break;
default:
break;
}
}
unsigned short X86CommonArchitecture::GetInstructionOpcode(const xed_decoded_inst_t* const xedd, const xed_operand_values_t* const ov, vector<InstructionTextToken>& result) const
{
string opcode = "";
if (xed_decoded_inst_has_mpx_prefix(xedd))
opcode += "BND ";
if (xed_decoded_inst_is_xacquire(xedd))
opcode += "XACQUIRE ";
if (xed_decoded_inst_is_xrelease(xedd))
opcode += "XRELEASE ";
if (xed_operand_values_has_lock_prefix(ov))
opcode += "LOCK ";
if (xed_operand_values_has_real_rep(ov))
{
if (xed_operand_values_has_rep_prefix(ov))
opcode += "REP ";
if (xed_operand_values_has_repne_prefix(ov))
opcode += "REPNE ";
}
else if (xed_operand_values_branch_not_taken_hint(ov))
opcode += "HINT-NOT-TAKEN ";
else if (xed_operand_values_branch_taken_hint(ov))
opcode += "HINT-TAKEN ";
switch (m_disassembly_options.df)
{
case DF_INTEL:
opcode += string(xed_iform_to_iclass_string_intel(xed_decoded_inst_get_iform_enum(xedd)));
break;
case DF_BN_INTEL:
// To match asmx86 disassembly
switch (xed_decoded_inst_get_iclass(xedd))
{
case XED_ICLASS_RET_NEAR:
opcode += "RETN";
break;
case XED_ICLASS_JZ:
opcode += "JE";
break;
case XED_ICLASS_JNZ:
opcode += "JNE";
break;
case XED_ICLASS_JNB:
opcode += "JAE";
break;
case XED_ICLASS_JNBE:
opcode += "JA";
break;
case XED_ICLASS_JP:
opcode += "JPE";
break;
case XED_ICLASS_JNP:
opcode += "JPO";
break;
case XED_ICLASS_JNL:
opcode += "JGE";
break;
case XED_ICLASS_JNLE:
opcode += "JG";
break;
case XED_ICLASS_SETNB:
opcode += "SETAE";
break;
case XED_ICLASS_SETZ:
opcode += "SETE";
break;
case XED_ICLASS_SETNZ:
opcode += "SETNE";
break;
case XED_ICLASS_SETNBE:
opcode += "SETA";
break;
case XED_ICLASS_SETP:
opcode += "SETPE";
break;
case XED_ICLASS_SETNP:
opcode += "SETPO";
break;
case XED_ICLASS_SETNL:
opcode += "SETGE";
break;
case XED_ICLASS_SETNLE:
opcode += "SETG";
break;
case XED_ICLASS_CMOVNB:
opcode += "CMOVAE";
break;
case XED_ICLASS_CMOVZ:
opcode += "CMOVE";
break;
case XED_ICLASS_CMOVNZ:
opcode += "CMOVNE";
break;
case XED_ICLASS_CMOVNBE:
opcode += "CMOVA";
break;
case XED_ICLASS_CMOVP:
opcode += "CMOVPE";
break;
case XED_ICLASS_CMOVNP:
opcode += "CMOVPO";
break;
case XED_ICLASS_CMOVNL:
opcode += "CMOVGE";
break;
case XED_ICLASS_CMOVNLE:
opcode += "CMOVG";
break;
default:
opcode += string(xed_iform_to_iclass_string_intel(xed_decoded_inst_get_iform_enum(xedd)));
}
break;
case DF_ATT:
opcode += string(xed_iform_to_iclass_string_att(xed_decoded_inst_get_iform_enum(xedd)));
break;
case DF_XED:
opcode += string(xed_iclass_enum_t2str(xed_decoded_inst_get_iclass(xedd)));
break;
default:
LogError("Invalid Disassembly Flavor");
}
if (m_disassembly_options.lowerCase)
for (char& c : opcode)
c = tolower(c);
else
for (char& c : opcode)
c = toupper(c);
result.emplace_back(InstructionToken, opcode);
return (unsigned short)opcode.length();
}
void X86CommonArchitecture::GetInstructionPadding(const unsigned int instruction_name_length, vector<InstructionTextToken>& result) const
{
string padding = "";
const short min = 7 < instruction_name_length ? 7 : instruction_name_length;
for (unsigned short delim = 0; delim < (8 - min); ++delim)
padding += ' ';
result.emplace_back(TextToken, padding);
}
// (in theory) Exactly how XED wants the world to see x86
void X86CommonArchitecture::GetOperandTextIntel(const xed_decoded_inst_t* const xedd, const uint64_t addr, const size_t len, const xed_operand_values_t* const ov, const xed_inst_t* const xi, vector<InstructionTextToken>& result) const
{
xed_reg_enum_t extra_index_operand = XED_REG_INVALID;
// Get operands
for (unsigned int opIndex = 0; opIndex < xed_inst_noperands(xi); ++opIndex)
{
const xed_operand_t* op = xed_inst_operand(xi, opIndex);
const xed_operand_enum_t op_name = xed_operand_name(op);
// XED's suppressed operands shouln't be represented in Intel syntax
if (xed_operand_operand_visibility(op) == XED_OPVIS_SUPPRESSED)
{
if ((xed_decoded_inst_get_category(xedd) == XED_CATEGORY_STRINGOP) &&
(op_name == XED_OPERAND_MEM0 || op_name == XED_OPERAND_MEM1))
{
if (op_name == XED_OPERAND_MEM1)
result.emplace_back(OperandSeparatorToken, m_disassembly_options.separator);
}
else
continue;
}
switch(op_name)
{
case XED_OPERAND_REG0:
case XED_OPERAND_REG1:
case XED_OPERAND_REG2:
case XED_OPERAND_REG3:
case XED_OPERAND_REG4:
case XED_OPERAND_REG5:
case XED_OPERAND_REG6:
case XED_OPERAND_REG7:
case XED_OPERAND_REG8:
{
string reg = "";
const xed_reg_enum_t xedReg = xed_decoded_inst_get_reg(xedd, op_name);
if ((xedReg >= XED_REG_X87_FIRST) && (xedReg <= XED_REG_X87_LAST))
{
reg += "ST";
reg += ('0' + (xedReg-XED_REG_X87_FIRST));
}
else
{
reg += xed_reg_enum_t2str(xedReg);
}
if (m_disassembly_options.lowerCase)
for (char& c : reg)
c = tolower(c);
result.emplace_back(RegisterToken, reg);
break;
}
case XED_OPERAND_AGEN:
case XED_OPERAND_MEM0:
{
GetAddressSizeToken(xed_decoded_inst_operand_length_bits(xedd, opIndex) / 8, result, m_disassembly_options.lowerCase);
if (m_disassembly_options.lowerCase)
result.emplace_back(KeywordToken, "ptr ");
else
result.emplace_back(KeywordToken, "PTR ");
result.emplace_back(BraceToken, "[");
// Segment
const xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 0);
const bool validSegment = (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 0));
if (validSegment)
{
string seg_str(xed_reg_enum_t2str(seg));
if (m_disassembly_options.lowerCase)
for (char& c : seg_str)
c = tolower(c);
result.emplace_back(RegisterToken, seg_str);
result.emplace_back(OperationToken, ":");
}
bool started = false;
const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 0);
int64_t disp = xed_decoded_inst_get_memory_displacement(xedd, 0);
if ((base != XED_REG_INVALID) && !((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP)))
{
string base_str(xed_reg_enum_t2str(base));
if (m_disassembly_options.lowerCase)
for (char& c : base_str)
c = tolower(c);
result.emplace_back(RegisterToken, base_str);
started = true;
}
else if ((base == XED_REG_RIP) || (base == XED_REG_EIP) || (base == XED_REG_IP))
{
if (xed_operand_values_has_memory_displacement(ov))
disp += addr + len;
else
disp = addr + len;
stringstream sstream;
if (m_disassembly_options.lowerCase)
sstream << "0x" << hex << nouppercase << disp;
else
sstream << "0x" << hex << uppercase << disp;
result.emplace_back(CodeRelativeAddressToken, sstream.str(), disp, GetAddressSize());
result.emplace_back(EndMemoryOperandToken, "");
result.emplace_back(BraceToken, "]");
break;
}
const xed_reg_enum_t index = xed_decoded_inst_get_index_reg(xedd, 0);
if (index != XED_REG_INVALID)
{
if (xed_decoded_inst_get_attribute(xedd, XED_ATTRIBUTE_INDEX_REG_IS_POINTER))
{
// MPX BNDLDX/BNDSTX instr are unusual in that they use
// the index reg as distinct operand.
extra_index_operand = index;
}
else // normal path
{
if (started)
result.emplace_back(OperationToken, "+");
started = true;
string index_str(xed_reg_enum_t2str(index));
if (m_disassembly_options.lowerCase)
for (char& c : index_str)
c = tolower(c);
result.emplace_back(RegisterToken, index_str);
const unsigned int scale = xed_decoded_inst_get_scale(xedd, 0);
if (scale != 1)
{
result.emplace_back(OperationToken, "*");
stringstream sstream;
sstream << scale;
result.emplace_back(IntegerToken, sstream.str(), scale, 1);
}
}
}
const unsigned short disp_bytes = xed_decoded_inst_get_memory_displacement_width_bits(xedd, 0) / 8;
if (xed_operand_values_has_memory_displacement(ov) &&
((disp != 0) || (!started && validSegment)))
{
stringstream sstream;
sstream << "0x" << hex;
if (m_disassembly_options.lowerCase)
sstream << nouppercase;
else
sstream << uppercase;
if (started)
{
if (disp < 0)
{
result.emplace_back(OperationToken, "-");
disp = -disp;
}
else
result.emplace_back(OperationToken, "+");
if (disp_bytes == 2)
sstream << (uint16_t)disp;
else if (disp_bytes == 4)
sstream << (uint32_t)disp;
else if (disp_bytes == 8)
sstream << (uint64_t)disp;
else
sstream << disp;
result.emplace_back(IntegerToken, sstream.str(), disp, disp_bytes);
}
else
{
sstream << disp;
if (validSegment)
result.emplace_back(IntegerToken, sstream.str(), disp, GetAddressSize());
else
result.emplace_back(PossibleAddressToken, sstream.str(), disp, GetAddressSize());
}
}
else if (xed_operand_values_has_memory_displacement(ov) &&
((disp == 0) && (!started)))
{
result.emplace_back(IntegerToken, "0x0", disp, GetAddressSize());
}
result.emplace_back(EndMemoryOperandToken, "");
result.emplace_back(BraceToken, "]");
break;
}
case XED_OPERAND_MEM1:
{
GetAddressSizeToken(xed_decoded_inst_operand_length_bits(xedd, opIndex) / 8, result, m_disassembly_options.lowerCase);
if (m_disassembly_options.lowerCase)
result.emplace_back(KeywordToken, "ptr ");
else
result.emplace_back(KeywordToken, "PTR ");
// Segment
const xed_reg_enum_t seg = xed_decoded_inst_get_seg_reg(xedd, 1);
if (seg != XED_REG_INVALID && !xed_operand_values_using_default_segment(ov, 1))
{
string seg_str(xed_reg_enum_t2str(seg));
if (m_disassembly_options.lowerCase)
for (char& c : seg_str)
c = tolower(c);
result.emplace_back(RegisterToken, seg_str);
result.emplace_back(OperationToken, ":");
}
result.emplace_back(BraceToken, "[");
const xed_reg_enum_t base = xed_decoded_inst_get_base_reg(xedd, 1);
if (base != XED_REG_INVALID)
{
string base_str(xed_reg_enum_t2str(base));
if (m_disassembly_options.lowerCase)
for (char& c : base_str)
c = tolower(c);
result.emplace_back(RegisterToken, base_str);
}
result.emplace_back(EndMemoryOperandToken, "");
result.emplace_back(BraceToken, "]");
break;
}
case XED_OPERAND_IMM0:
{
const size_t addrSize = xed_decoded_inst_get_machine_mode_bits(xedd) / 8;
const unsigned int immediateSize = xed_decoded_inst_get_operand_width(xedd) / 8;
stringstream sstream;
sstream << "0x" << hex;
if (m_disassembly_options.lowerCase)
sstream << nouppercase;
else
sstream << uppercase;
if (xed_decoded_inst_get_immediate_is_signed(xedd) && (immediateSize != 1))
{
const int64_t immediateValue = xed_decoded_inst_get_signed_immediate(xedd);