Internal changes

PiperOrigin-RevId: 755898792
Change-Id: I708cb058a2247722c1067c88f9c4278305c110a8

Author: rjogrady

fleetbench/parallel/parallel_bench.py

@@ -27,10 +27,11 @@
 from absl import flags
 from absl import logging
 
+# pylint:disable=line-too-long
 from fleetbench.parallel import cpu
 from fleetbench.parallel import parallel_bench_lib
 from fleetbench.parallel import weights
-
+# pylint:enable=line-too-long
 
 _CPU_AFFINITY = flags.DEFINE_bool(
     "cpu_affinity", True, "Bind each worker to a single CPU."