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hdmi_ao_cec.c
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2053 lines (1797 loc) · 57.7 KB
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/*
* drivers/amlogic/cec/hdmi_ao_cec.c
*
* Copyright (C) 2015 Amlogic, Inc. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
*/
#include <linux/version.h>
#include <linux/module.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/input.h>
#include <linux/kernel.h>
#include <linux/kthread.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/fs.h>
#include <linux/init.h>
#include <linux/device.h>
#include <linux/mm.h>
#include <linux/major.h>
#include <linux/platform_device.h>
#include <linux/mutex.h>
#include <linux/cdev.h>
#include <asm/irq.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/list.h>
#include <linux/spinlock.h>
#include <linux/spinlock_types.h>
#include <linux/switch.h>
#include <linux/workqueue.h>
#include <linux/timer.h>
#include <linux/uaccess.h>
#include <linux/delay.h>
#include <linux/amlogic/tvin/tvin.h>
#include <linux/wakelock_android.h>
#include <linux/amlogic/hdmi_tx/hdmi_tx_cec_20.h>
#include <linux/amlogic/hdmi_tx/hdmi_tx_module.h>
#include <linux/of.h>
#include <linux/pinctrl/consumer.h>
#include <linux/of_irq.h>
#include "hdmi_ao_cec.h"
#include <linux/notifier.h>
#include <linux/reboot.h>
#include <linux/amlogic/pm.h>
#include <linux/of_address.h>
#ifdef CONFIG_HAS_EARLYSUSPEND
#include <linux/earlysuspend.h>
static struct early_suspend aocec_suspend_handler;
#endif
#define CEC_FRAME_DELAY msecs_to_jiffies(400)
#define CEC_DEV_NAME "cec"
#define DEV_TYPE_TX 4
#define DEV_TYPE_RX 0
#define CEC_EARLY_SUSPEND (1 << 0)
#define CEC_DEEP_SUSPEND (1 << 1)
/* global struct for tx and rx */
struct ao_cec_dev {
unsigned long dev_type;
unsigned int port_num;
unsigned int arc_port;
unsigned int hal_flag;
unsigned int phy_addr;
unsigned int port_seq;
unsigned long irq_cec;
void __iomem *exit_reg;
void __iomem *cec_reg;
void __iomem *hdmi_rxreg;
struct hdmitx_dev *tx_dev;
struct workqueue_struct *cec_thread;
struct device *dbg_dev;
struct delayed_work cec_work;
struct completion rx_ok;
struct completion tx_ok;
spinlock_t cec_reg_lock;
struct mutex cec_mutex;
#ifdef CONFIG_PM
int cec_suspend;
#endif
struct vendor_info_data v_data;
struct cec_global_info_t cec_info;
};
static int phy_addr_test;
/* from android cec hal */
enum {
HDMI_OPTION_WAKEUP = 1,
HDMI_OPTION_ENABLE_CEC = 2,
HDMI_OPTION_SYSTEM_CEC_CONTROL = 3,
HDMI_OPTION_SET_LANG = 5,
};
static struct ao_cec_dev *cec_dev;
static int cec_tx_result;
static unsigned char rx_msg[MAX_MSG];
static unsigned char rx_len;
static unsigned int new_msg;
bool cec_msg_dbg_en = 0;
#define CEC_ERR(format, args...) \
{if (cec_dev->dbg_dev) \
dev_err(cec_dev->dbg_dev, "%s(): " format, __func__, ##args); \
}
#define CEC_INFO(format, args...) \
{if (cec_msg_dbg_en && cec_dev->dbg_dev) \
dev_info(cec_dev->dbg_dev, "%s(): " format, __func__, ##args); \
}
static unsigned char msg_log_buf[128] = { 0 };
#define waiting_aocec_free() \
do {\
unsigned long cnt = 0;\
while (readl(cec_dev->cec_reg + AO_CEC_RW_REG) & (1<<23)) {\
if (3500 == cnt++) { \
pr_info("waiting aocec free time out.\n");\
break;\
} \
} \
} while (0)
#define HR_DELAY(n) (ktime_set(0, n * 1000 * 1000))
__u16 cec_key_map[160] = {
KEY_ENTER, KEY_UP, KEY_DOWN, KEY_LEFT, KEY_RIGHT, 0 , 0 , 0 ,//0x00
0 , KEY_HOMEPAGE , KEY_MENU, 0, 0, KEY_BACK, 0, 0,
0 , 0, 0, 0, 0, 0, 0, 0,//0x10
0 , 0, 0, 0, 0, 0, 0, 0,
KEY_0 , KEY_1, KEY_2, KEY_3,KEY_4, KEY_5, KEY_6, KEY_7,//0x20
KEY_8 , KEY_9, KEY_DOT, 0, 0, 0, 0, 0,
KEY_CHANNELUP , KEY_CHANNELDOWN, KEY_CHANNEL, 0, 0, 0, 0, 0,//0x30
0 , 0, 0, 0, 0, 0, 0, 0,
KEY_POWER , KEY_VOLUMEUP, KEY_VOLUMEDOWN, KEY_MUTE, KEY_PLAYPAUSE, KEY_STOP, KEY_PLAYPAUSE, KEY_RECORD,//0x40
KEY_REWIND, KEY_FASTFORWARD, KEY_EJECTCD, KEY_NEXTSONG, KEY_PREVIOUSSONG, 0, 0, 0,
0 , 0, 0, KEY_PROGRAM, 0, 0, 0, 0,//0x50
0 , 0, 0, 0, 0, 0, 0, 0,
KEY_PLAYCD, KEY_PLAYPAUSE, KEY_RECORD, KEY_PAUSECD, KEY_STOPCD, KEY_MUTE, 0, KEY_TUNER,//0x60
0 , KEY_MEDIA, 0, 0, KEY_POWER, 0, 0, 0,
0 , KEY_BLUE, KEY_RED, KEY_GREEN, KEY_YELLOW, 0, 0, 0,//0x70
0 , 0, 0, 0, 0, 0, 0, 0x2fd,
0 , 0, 0, 0, 0, 0, 0, 0,//0x80
0 , 0, 0, 0, 0, 0, 0, 0,
0 , KEY_EXIT, 0, 0, 0, 0, KEY_PVR, 0,//0x90 //samsung vendor buttons return and channel_list
0 , 0, 0, 0, 0, 0, 0, 0,
};
struct hrtimer cec_key_timer;
static int last_key_irq = -1;
static int key_value = 1;
enum hrtimer_restart cec_key_up(struct hrtimer *timer)
{
if (key_value == 1){
input_event(cec_dev->cec_info.remote_cec_dev,
EV_KEY, cec_key_map[last_key_irq], 0);
}
input_sync(cec_dev->cec_info.remote_cec_dev);
CEC_INFO("last:%d up\n", cec_key_map[last_key_irq]);
key_value = 2;
return HRTIMER_NORESTART;
}
void cec_user_control_pressed_irq(unsigned char message_irq)
{
if (message_irq < 160) {
CEC_INFO("Key pressed: %d\n", message_irq);
input_event(cec_dev->cec_info.remote_cec_dev, EV_KEY,
cec_key_map[message_irq], key_value);
input_sync(cec_dev->cec_info.remote_cec_dev);
last_key_irq = message_irq;
hrtimer_start(&cec_key_timer, HR_DELAY(200), HRTIMER_MODE_REL);
CEC_INFO(":key map:%d\n", cec_key_map[message_irq]);
}
}
void cec_user_control_released_irq(void)
{
/*
* key must be valid
*/
if (last_key_irq != -1) {
CEC_INFO("Key released: %d\n",last_key_irq);
hrtimer_cancel(&cec_key_timer);
input_event(cec_dev->cec_info.remote_cec_dev,
EV_KEY, cec_key_map[last_key_irq], 0);
input_sync(cec_dev->cec_info.remote_cec_dev);
key_value = 1;
}
}
void cec_set_reg_bits(unsigned int addr, unsigned int value,
unsigned int offset, unsigned int len)
{
unsigned int data32 = 0;
data32 = readl(cec_dev->cec_reg + addr);
data32 &= ~(((1 << len) - 1) << offset);
data32 |= (value & ((1 << len) - 1)) << offset;
writel(data32, cec_dev->cec_reg + addr);
}
unsigned int aocec_rd_reg(unsigned long addr)
{
unsigned int data32;
unsigned long flags;
waiting_aocec_free();
spin_lock_irqsave(&cec_dev->cec_reg_lock, flags);
data32 = 0;
data32 |= 0 << 16; /* [16] cec_reg_wr */
data32 |= 0 << 8; /* [15:8] cec_reg_wrdata */
data32 |= addr << 0; /* [7:0] cec_reg_addr */
writel(data32, cec_dev->cec_reg + AO_CEC_RW_REG);
waiting_aocec_free();
data32 = ((readl(cec_dev->cec_reg + AO_CEC_RW_REG)) >> 24) & 0xff;
spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags);
return data32;
} /* aocec_rd_reg */
void aocec_wr_reg(unsigned long addr, unsigned long data)
{
unsigned long data32;
unsigned long flags;
waiting_aocec_free();
spin_lock_irqsave(&cec_dev->cec_reg_lock, flags);
data32 = 0;
data32 |= 1 << 16; /* [16] cec_reg_wr */
data32 |= data << 8; /* [15:8] cec_reg_wrdata */
data32 |= addr << 0; /* [7:0] cec_reg_addr */
writel(data32, cec_dev->cec_reg + AO_CEC_RW_REG);
spin_unlock_irqrestore(&cec_dev->cec_reg_lock, flags);
} /* aocec_wr_only_reg */
static void cec_enable_irq(void)
{
cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x6, 0, 3);
CEC_INFO("enable:int mask:0x%x\n",
readl(cec_dev->cec_reg + AO_CEC_INTR_MASKN));
}
static void cec_hw_buf_clear(void)
{
aocec_wr_reg(CEC_RX_MSG_CMD, RX_DISABLE);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
aocec_wr_reg(CEC_RX_CLEAR_BUF, 1);
aocec_wr_reg(CEC_TX_CLEAR_BUF, 1);
udelay(100);
aocec_wr_reg(CEC_RX_CLEAR_BUF, 0);
aocec_wr_reg(CEC_TX_CLEAR_BUF, 0);
udelay(100);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
}
void cec_logicaddr_clear(void)
{
int i;
for (i = 0; i < 5; i++) {
aocec_wr_reg((CEC_LOGICAL_ADDR0 + i), 0);
cec_dev->cec_info.log_addr[i] = 0;
udelay(100);
}
cec_hw_buf_clear();
}
void cec_logicaddr_setByMask(unsigned int mask)
{
int i, j;
int reg = 0;
int primary = -1;
// ignore reserved device type
const int device_types[5] = {CEC_RECORDING_DEVICE,
CEC_PLAYBACK_DEVICE,
CEC_TUNER_DEVICE,
CEC_AUDIO_SYSTEM_DEVICE,
CEC_DISPLAY_DEVICE|CEC_UNREGISTERED
};
mask &= 0xffff;
if (mask == 0) {
cec_logicaddr_clear();
return;
}
for (i = CEC_TV_ADDR; i <= CEC_UNREGISTERED_ADDR; i++) {
if (reg > 4) {
break;
}
if ((mask & 1<<i) == 1<<i) {
for (j = 0; j <= sizeof(device_types); j++) {
// Max. one of each type
if (1<<i & device_types[j]) {
CEC_INFO("ADDING LA:0x%d reg:0x%d\n", i,
(CEC_LOGICAL_ADDR0 + reg));
mask &= ~(mask & device_types[j]);
cec_dev->cec_info.log_addr[reg] = i;
cec_logicaddr_set(i, (CEC_LOGICAL_ADDR0 + reg));
if (primary == -1);
primary = i;
cec_logicaddr_config(primary, 1);
reg++;
break;
}
}
}
}
}
void cec_logicaddr_set(int logicaddr, int logreg)
{
aocec_wr_reg(logreg, 0);
cec_hw_buf_clear();
aocec_wr_reg(logreg, (logicaddr & 0xf));
udelay(100);
aocec_wr_reg(logreg, (0x1 << 4) | (logicaddr & 0xf));
if (cec_msg_dbg_en)
CEC_INFO("set logical addr:0x%x\n",
aocec_rd_reg(logreg));
}
static void cec_hw_reset(void)
{
writel(0x1, cec_dev->cec_reg + AO_CEC_GEN_CNTL);
/* Enable gated clock (Normal mode). */
cec_set_reg_bits(AO_CEC_GEN_CNTL, 1, 1, 1);
/* Release SW reset */
udelay(100);
cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1);
/* Enable all AO_CEC interrupt sources */
cec_set_reg_bits(AO_CEC_INTR_MASKN, 0x6, 0, 3);
cec_logicaddr_set(cec_dev->cec_info.log_addr[0], CEC_LOGICAL_ADDR0);
/* Cec arbitration 3/5/7 bit time set. */
cec_arbit_bit_time_set(3, 0x118, 0);
cec_arbit_bit_time_set(5, 0x000, 0);
cec_arbit_bit_time_set(7, 0x2aa, 0);
CEC_INFO("hw reset :logical addr:0x%x\n",
aocec_rd_reg(CEC_LOGICAL_ADDR0));
}
void cec_rx_buf_clear(void)
{
aocec_wr_reg(CEC_RX_CLEAR_BUF, 0x1);
aocec_wr_reg(CEC_RX_CLEAR_BUF, 0x0);
CEC_INFO("rx buf clean\n");
}
int cec_rx_buf_check(void)
{
unsigned int rx_num_msg = aocec_rd_reg(CEC_RX_NUM_MSG);
if (rx_num_msg)
CEC_INFO("rx msg num:0x%02x\n", rx_num_msg);
return rx_num_msg;
}
int cec_ll_rx(unsigned char *msg, unsigned char *len)
{
int i;
int ret = -1;
int pos;
int rx_stat;
rx_stat = aocec_rd_reg(CEC_RX_MSG_STATUS);
if ((RX_DONE != rx_stat) || (1 != aocec_rd_reg(CEC_RX_NUM_MSG))) {
CEC_INFO("rx status:%x\n", rx_stat);
writel((1 << 2), cec_dev->cec_reg + AO_CEC_INTR_CLR);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_CURRENT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return ret;
}
*len = aocec_rd_reg(CEC_RX_MSG_LENGTH) + 1;
for (i = 0; i < (*len) && i < MAX_MSG; i++)
msg[i] = aocec_rd_reg(CEC_RX_MSG_0_HEADER + i);
ret = rx_stat;
/* ignore ping message */
if (cec_msg_dbg_en == 1 && *len > 1) {
pos = 0;
pos += sprintf(msg_log_buf + pos,
"CEC: rx msg len: %d dat: ", *len);
for (i = 0; i < (*len); i++)
pos += sprintf(msg_log_buf + pos, "%02x ", msg[i]);
pos += sprintf(msg_log_buf + pos, "\n");
msg_log_buf[pos] = '\0';
CEC_INFO("%s", msg_log_buf);
}
writel((1 << 2), cec_dev->cec_reg + AO_CEC_INTR_CLR);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_ACK_NEXT);
aocec_wr_reg(CEC_RX_MSG_CMD, RX_NO_OP);
return ret;
}
void cec_polling_online_dev(int log_addr, int *bool)
{
unsigned int r;
unsigned char msg[1];
int retry = 5;
msg[0] = (log_addr<<4) | log_addr;
/* set broadcast address first */
cec_logicaddr_set(0xf, CEC_LOGICAL_ADDR0);
if (cec_msg_dbg_en == 1)
CEC_INFO("CEC_LOGICAL_ADDR0:0x%i\n",
aocec_rd_reg(CEC_LOGICAL_ADDR0));
while (retry) {
r = cec_ll_tx(msg, 1);
if (r == CEC_FAIL_BUSY) {
retry--;
CEC_INFO("try log addr %x busy, retry:%d\n",
log_addr, retry);
/*
* try to reset CEC if tx busy is found
*/
cec_hw_reset();
} else
break;
}
if (r == CEC_FAIL_NACK) {
*bool = 0;
} else if (r == CEC_FAIL_NONE) {
*bool = 1;
}
CEC_INFO("CEC: poll online logic device: 0x%x BOOL: %d\n",
log_addr, *bool);
}
/************************ cec arbitration cts code **************************/
/* using the cec pin as fiq gpi to assist the bus arbitration */
/* return value: 1: successful 0: error */
static int cec_ll_trigle_tx(const unsigned char *msg, int len)
{
int i;
unsigned int n;
int pos;
int reg;
unsigned int j = 20;
unsigned tx_stat;
static int cec_timeout_cnt = 1;
int flag = 0;
while (1) {
tx_stat = aocec_rd_reg(CEC_TX_MSG_STATUS);
if (tx_stat != TX_BUSY)
break;
if (!flag && tx_stat == TX_BUSY) {
CEC_INFO("TX is busy. Sending TX_ABORT\n");
aocec_wr_reg(CEC_TX_MSG_CMD, TX_ABORT);
flag = 1;
}
if (!(j--)) {
CEC_INFO("TX is still busy. Sending TX_NO_OP\n");
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
cec_timeout_cnt++;
if (cec_timeout_cnt > 0x08) {
cec_hw_reset();
break;
}
}
msleep(20);
}
reg = aocec_rd_reg(CEC_TX_MSG_STATUS);
if (reg == TX_IDLE || reg == TX_DONE) {
for (i = 0; i < len; i++)
aocec_wr_reg(CEC_TX_MSG_0_HEADER + i, msg[i]);
aocec_wr_reg(CEC_TX_MSG_LENGTH, len-1);
aocec_wr_reg(CEC_TX_MSG_CMD, TX_REQ_CURRENT);
if (cec_msg_dbg_en == 1) {
pos = 0;
pos += sprintf(msg_log_buf + pos,
"CEC: tx msg len: %d dat: ", len);
for (n = 0; n < len; n++) {
pos += sprintf(msg_log_buf + pos,
"%02x ", msg[n]);
}
pos += sprintf(msg_log_buf + pos, "\n");
msg_log_buf[pos] = '\0';
pr_info("%s", msg_log_buf);
}
cec_timeout_cnt = 0;
return 0;
}
return -1;
}
void tx_irq_handle(void)
{
unsigned tx_status = aocec_rd_reg(CEC_TX_MSG_STATUS);
switch (tx_status) {
case TX_DONE:
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
cec_tx_result = 0;
complete(&cec_dev->tx_ok);
break;
case TX_BUSY:
CEC_ERR("TX_BUSY\n");
break;
case TX_ERROR:
if (cec_msg_dbg_en == 1)
CEC_ERR("TX ERROR!!!\n");
if (RX_ERROR == aocec_rd_reg(CEC_RX_MSG_STATUS)) {
cec_hw_reset();
} else {
aocec_wr_reg(CEC_TX_MSG_CMD, TX_NO_OP);
}
cec_tx_result = 1;
complete(&cec_dev->tx_ok);
break;
case TX_IDLE:
break;
default:
break;
}
writel((1 << 1), cec_dev->cec_reg + AO_CEC_INTR_CLR);
}
/* Return value: < 0: fail, > 0: success */
int cec_ll_tx(const unsigned char *msg, unsigned char len)
{
int ret = 0;
int timeout = msecs_to_jiffies(1000);
if (len == 0)
return CEC_FAIL_NONE;
mutex_lock(&cec_dev->cec_mutex);
/*
* do not send messanges if tv is not support CEC
*/
ret = cec_ll_trigle_tx(msg, len);
if (ret < 0) {
/* we should increase send idx if busy */
CEC_INFO("tx busy\n");
mutex_unlock(&cec_dev->cec_mutex);
return CEC_FAIL_BUSY;
}
cec_tx_result = 0;
ret = wait_for_completion_timeout(&cec_dev->tx_ok, timeout);
if (ret <= 0) {
/* timeout of interrupt */
ret = CEC_FAIL_OTHER;
CEC_INFO("tx timeout\n");
} else {
if (cec_tx_result)
ret = CEC_FAIL_NACK;
else
ret = CEC_FAIL_NONE;
}
mutex_unlock(&cec_dev->cec_mutex);
return ret;
}
/* -------------------------------------------------------------------------- */
/* AO CEC0 config */
/* -------------------------------------------------------------------------- */
void ao_cec_init(void)
{
unsigned long data32;
unsigned int reg;
/* Assert SW reset AO_CEC */
reg = readl(cec_dev->cec_reg + AO_CRT_CLK_CNTL1);
/* 24MHz/ (731 + 1) = 32786.885Hz */
reg &= ~(0x7ff << 16);
reg |= (731 << 16); /* divider from 24MHz */
reg |= (0x1 << 26);
reg &= ~(0x800 << 16); /* select divider */
writel(reg, cec_dev->cec_reg + AO_CRT_CLK_CNTL1);
data32 = 0;
data32 |= 0 << 1; /* [2:1] cntl_clk: */
/* 0=Disable clk (Power-off mode); */
/* 1=Enable gated clock (Normal mode); */
/* 2=Enable free-run clk (Debug mode). */
data32 |= 1 << 0; /* [0] sw_reset: 1=Reset */
writel(data32, cec_dev->cec_reg + AO_CEC_GEN_CNTL);
/* Enable gated clock (Normal mode). */
cec_set_reg_bits(AO_CEC_GEN_CNTL, 1, 1, 1);
/* Release SW reset */
cec_set_reg_bits(AO_CEC_GEN_CNTL, 0, 0, 1);
/* Enable all AO_CEC interrupt sources */
cec_enable_irq();
}
void cec_arbit_bit_time_set(unsigned bit_set, unsigned time_set, unsigned flag)
{ /* 11bit:bit[10:0] */
if (flag) {
CEC_INFO("bit_set:0x%x;time_set:0x%x\n",
bit_set, time_set);
}
switch (bit_set) {
case 3:
/* 3 bit */
if (flag) {
CEC_INFO("read 3 bit:0x%x%x\n",
aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT10_8),
aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT7_0));
}
aocec_wr_reg(AO_CEC_TXTIME_4BIT_BIT7_0, time_set & 0xff);
aocec_wr_reg(AO_CEC_TXTIME_4BIT_BIT10_8, (time_set >> 8) & 0x7);
if (flag) {
CEC_INFO("write 3 bit:0x%x%x\n",
aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT10_8),
aocec_rd_reg(AO_CEC_TXTIME_4BIT_BIT7_0));
}
break;
/* 5 bit */
case 5:
if (flag) {
CEC_INFO("read 5 bit:0x%x%x\n",
aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT10_8),
aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT7_0));
}
aocec_wr_reg(AO_CEC_TXTIME_2BIT_BIT7_0, time_set & 0xff);
aocec_wr_reg(AO_CEC_TXTIME_2BIT_BIT10_8, (time_set >> 8) & 0x7);
if (flag) {
CEC_INFO("write 5 bit:0x%x%x\n",
aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT10_8),
aocec_rd_reg(AO_CEC_TXTIME_2BIT_BIT7_0));
}
break;
/* 7 bit */
case 7:
if (flag) {
CEC_INFO("read 7 bit:0x%x%x\n",
aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT10_8),
aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT7_0));
}
aocec_wr_reg(AO_CEC_TXTIME_17MS_BIT7_0, time_set & 0xff);
aocec_wr_reg(AO_CEC_TXTIME_17MS_BIT10_8, (time_set >> 8) & 0x7);
if (flag) {
CEC_INFO("write 7 bit:0x%x%x\n",
aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT10_8),
aocec_rd_reg(AO_CEC_TXTIME_17MS_BIT7_0));
}
break;
default:
break;
}
}
static unsigned int ao_cec_intr_stat(void)
{
return readl(cec_dev->cec_reg + AO_CEC_INTR_STAT);
}
unsigned int cec_intr_stat(void)
{
return ao_cec_intr_stat();
}
/*
*wr_flag: 1 write; value valid
* 0 read; value invalid
*/
unsigned int cec_config(unsigned int value, bool wr_flag)
{
if (wr_flag)
cec_set_reg_bits(AO_DEBUG_REG0, value, 0, 8);
return readl(cec_dev->cec_reg + AO_DEBUG_REG0);
}
/*
*wr_flag:1 write; value valid
* 0 read; value invalid
*/
unsigned int cec_phyaddr_config(unsigned int value, bool wr_flag)
{
if (wr_flag)
cec_set_reg_bits(AO_DEBUG_REG1, value, 0, 16);
return readl(cec_dev->cec_reg + AO_DEBUG_REG1);
}
/*
*wr_flag:1 write; value valid
* 0 read; value invalid
*/
unsigned int cec_logicaddr_config(unsigned int value, bool wr_flag)
{
if (wr_flag)
cec_set_reg_bits(AO_DEBUG_REG3, value, 0, 8);
return readl(cec_dev->cec_reg + AO_DEBUG_REG3);
}
void cec_keep_reset(void)
{
writel(0x1, cec_dev->cec_reg + AO_CEC_GEN_CNTL);
}
/*
* cec hw module init befor allocate logical address
*/
static void cec_pre_init(void)
{
ao_cec_init();
cec_config(cec_dev->tx_dev->cec_func_config, 1);
cec_arbit_bit_time_set(3, 0x118, 0);
cec_arbit_bit_time_set(5, 0x000, 0);
cec_arbit_bit_time_set(7, 0x2aa, 0);
}
static int cec_late_check_rx_buffer(void)
{
int ret;
struct delayed_work *dwork = &cec_dev->cec_work;
ret = cec_rx_buf_check();
if (!ret)
return 0;
/*
* start another check if rx buffer is full
*/
if ((-1) == cec_ll_rx(rx_msg, &rx_len)) {
CEC_INFO("buffer got unrecorgnized msg\n");
cec_rx_buf_clear();
return 0;
} else {
mod_delayed_work(cec_dev->cec_thread, dwork, 0);
return 1;
}
}
void cec_key_report(int suspend)
{
input_event(cec_dev->cec_info.remote_cec_dev, EV_KEY, KEY_POWER, 1);
input_sync(cec_dev->cec_info.remote_cec_dev);
input_event(cec_dev->cec_info.remote_cec_dev, EV_KEY, KEY_POWER, 0);
input_sync(cec_dev->cec_info.remote_cec_dev);
if (!suspend)
CEC_INFO("== WAKE UP BY CEC ==\n")
else
CEC_INFO("== SLEEP by CEC==\n")
}
void cec_give_version(unsigned int dest)
{
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char msg[3];
if (0xf != dest) {
msg[0] = ((index & 0xf) << 4) | dest;
msg[1] = CEC_OC_CEC_VERSION;
msg[2] = CEC_VERSION_14A;
cec_ll_tx(msg, 3);
}
}
void cec_report_physical_address_smp(void)
{
unsigned char msg[5];
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char phy_addr_ab, phy_addr_cd;
phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff;
phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff;
msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR;
msg[1] = CEC_OC_REPORT_PHYSICAL_ADDRESS;
msg[2] = phy_addr_ab;
msg[3] = phy_addr_cd;
msg[4] = cec_dev->dev_type;
cec_ll_tx(msg, 5);
}
void cec_device_vendor_id(void)
{
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char msg[5];
unsigned int vendor_id;
vendor_id = cec_dev->v_data.vendor_id;
msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR;
msg[1] = CEC_OC_DEVICE_VENDOR_ID;
msg[2] = (vendor_id >> 16) & 0xff;
msg[3] = (vendor_id >> 8) & 0xff;
msg[4] = (vendor_id >> 0) & 0xff;
cec_ll_tx(msg, 5);
}
void cec_give_deck_status(unsigned int dest)
{
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char msg[3];
msg[0] = ((index & 0xf) << 4) | dest;
msg[1] = CEC_OC_DECK_STATUS;
msg[2] = 0x1a;
cec_ll_tx(msg, 3);
}
void cec_menu_status_smp(int dest, int status)
{
unsigned char msg[3];
unsigned char index = cec_dev->cec_info.log_addr[0];
msg[0] = ((index & 0xf) << 4) | dest;
msg[1] = CEC_OC_MENU_STATUS;
if (status == DEVICE_MENU_ACTIVE)
msg[2] = DEVICE_MENU_ACTIVE;
else
msg[2] = DEVICE_MENU_INACTIVE;
cec_ll_tx(msg, 3);
}
void cec_imageview_on_smp(void)
{
unsigned char msg[2];
unsigned char index = cec_dev->cec_info.log_addr[0];
msg[0] = ((index & 0xf) << 4) | CEC_TV_ADDR;
msg[1] = CEC_OC_IMAGE_VIEW_ON;
cec_ll_tx(msg, 2);
}
void cec_get_menu_language_smp(void)
{
unsigned char msg[2];
unsigned char index = cec_dev->cec_info.log_addr[0];
msg[0] = ((index & 0xf) << 4) | CEC_TV_ADDR;
msg[1] = CEC_OC_GET_MENU_LANGUAGE;
cec_ll_tx(msg, 2);
}
void cec_inactive_source(int dest)
{
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char msg[4];
unsigned char phy_addr_ab, phy_addr_cd;
phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff;
phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff;
msg[0] = ((index & 0xf) << 4) | dest;
msg[1] = CEC_OC_INACTIVE_SOURCE;
msg[2] = phy_addr_ab;
msg[3] = phy_addr_cd;
cec_ll_tx(msg, 4);
}
void cec_set_osd_name(int dest)
{
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char osd_len = strlen(cec_dev->cec_info.osd_name);
unsigned char msg[16];
if (0xf != dest) {
msg[0] = ((index & 0xf) << 4) | dest;
msg[1] = CEC_OC_SET_OSD_NAME;
memcpy(&msg[2], cec_dev->cec_info.osd_name, osd_len);
cec_ll_tx(msg, 2 + osd_len);
}
}
void cec_active_source_smp(void)
{
unsigned char msg[4];
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char phy_addr_ab;
unsigned char phy_addr_cd;
phy_addr_ab = (cec_dev->phy_addr >> 8) & 0xff;
phy_addr_cd = (cec_dev->phy_addr >> 0) & 0xff;
msg[0] = ((index & 0xf) << 4) | CEC_BROADCAST_ADDR;
msg[1] = CEC_OC_ACTIVE_SOURCE;
msg[2] = phy_addr_ab;
msg[3] = phy_addr_cd;
cec_ll_tx(msg, 4);
}
void cec_set_stream_path(unsigned char *msg)
{
unsigned int phy_addr_active;
phy_addr_active = (unsigned int)(msg[2] << 8 | msg[3]);
if (phy_addr_active == cec_dev->phy_addr) {
cec_active_source_smp();
/*
* some types of TV such as panasonic need to send menu status,
* otherwise it will not send remote key event to control
* device's menu
*/
cec_menu_status_smp(msg[0] >> 4, DEVICE_MENU_ACTIVE);
}
}
void cec_report_power_status(int dest, int status)
{
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char msg[3];
msg[0] = ((index & 0xf) << 4) | dest;
msg[1] = CEC_OC_REPORT_POWER_STATUS;
msg[2] = status;
cec_ll_tx(msg, 3);
}
void cec_send_simplink_alive(void)
{
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char msg[4];
msg[0] = ((index & 0xf) << 4) | CEC_TV_ADDR;
msg[1] = CEC_OC_VENDOR_COMMAND;
msg[2] = 0x2;
msg[3] = 0x5;
cec_ll_tx(msg, 4);
}
void cec_send_simplink_ack(void)
{
unsigned char index = cec_dev->cec_info.log_addr[0];
unsigned char msg[4];
msg[0] = ((index & 0xf) << 4) | CEC_TV_ADDR;
msg[1] = CEC_OC_VENDOR_COMMAND;
msg[2] = 0x5;
msg[3] = 0x1;
cec_ll_tx(msg, 4);
}
int cec_node_init(struct hdmitx_dev *hdmitx_device)
{
unsigned char a, b, c, d;
int i, bool = 0;
int phy_addr_ok = 1;
const enum _cec_log_dev_addr_e player_dev[3] = {
CEC_RECORDING_DEVICE_1_ADDR,
CEC_RECORDING_DEVICE_2_ADDR,
CEC_RECORDING_DEVICE_3_ADDR,
};
unsigned long cec_phy_addr;
/* If no connect, return directly */
if ((hdmitx_device->cec_init_ready == 0) ||
(hdmitx_device->hpd_state == 0)) {
return -1;
}
a = hdmitx_device->hdmi_info.vsdb_phy_addr.a;
b = hdmitx_device->hdmi_info.vsdb_phy_addr.b;
c = hdmitx_device->hdmi_info.vsdb_phy_addr.c;
d = hdmitx_device->hdmi_info.vsdb_phy_addr.d;
/* Don't init if switched to libcec mode*/
if ((cec_dev->hal_flag & (1 << HDMI_OPTION_SYSTEM_CEC_CONTROL)))
return -1;