chisel.md

title	Chisel/FIRRTL Hardware Compiler Framework
description	A hardware design language that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs
authors	UC Berkeley
links	gh web docs chipsalliance/chisel3 https://www.chisel-lang.org/ https://www.chisel-lang.org/api/latest
categories	Languages Frameworks
tags	HDL scala soc generator RTL FIRRTL verilog
active	from 2010
licenses	Apache-2.0
talk	146

"Chisel adds hardware construction primitives to the Scala programming language, providing designers with the power of a modern programming language to write complex, parameterizable circuit generators that produce synthesizable Verilog. This generator methodology enables the creation of re-usable components and libraries, such as the FIFO queue and arbiters in the Chisel Standard Library, raising the level of abstraction in design while retaining fine-grained control."

• Currently, Chisel (Constructing Hardware in a Scala Embedded Language) is in its version 3 (first commit in 2015).

References:

• Previous Chisel repository (Chisel and Chisel 2 development, deprecated).
• FIRRTL (Flexible Internal Representation for RTL).