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2250 lines (1905 loc) · 53.9 KB
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// SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
// Copyright(c) 2015-18 Intel Corporation.
/*
* stream.c - SoundWire Bus stream operations.
*/
#include <linux/delay.h>
#include <linux/device.h>
#include <linux/init.h>
#include <linux/module.h>
#include <linux/mod_devicetable.h>
#include <linux/slab.h>
#include <linux/soundwire/sdw_registers.h>
#include <linux/soundwire/sdw.h>
#include <linux/soundwire/sdw_type.h>
#include <linux/string_choices.h>
#include <sound/soc.h>
#include "bus.h"
static int m_lane;
module_param(m_lane, int, 0444);
MODULE_PARM_DESC(m_lane, "Manager lane");
static int p_lane;
module_param(p_lane, int, 0444);
MODULE_PARM_DESC(p_lane, "Peripheral lane");
/*
* Array of supported rows and columns as per MIPI SoundWire Specification 1.1
*
* The rows are arranged as per the array index value programmed
* in register. The index 15 has dummy value 0 in order to fill hole.
*/
int sdw_rows[SDW_FRAME_ROWS] = {48, 50, 60, 64, 75, 80, 125, 147,
96, 100, 120, 128, 150, 160, 250, 0,
192, 200, 240, 256, 72, 144, 90, 180};
EXPORT_SYMBOL(sdw_rows);
int sdw_cols[SDW_FRAME_COLS] = {2, 4, 6, 8, 10, 12, 14, 16};
EXPORT_SYMBOL(sdw_cols);
int sdw_find_col_index(int col)
{
int i;
for (i = 0; i < SDW_FRAME_COLS; i++) {
if (sdw_cols[i] == col)
return i;
}
pr_warn("Requested column not found, selecting lowest column no: 2\n");
return 0;
}
EXPORT_SYMBOL(sdw_find_col_index);
int sdw_find_row_index(int row)
{
int i;
for (i = 0; i < SDW_FRAME_ROWS; i++) {
if (sdw_rows[i] == row)
return i;
}
pr_warn("Requested row not found, selecting lowest row no: 48\n");
return 0;
}
EXPORT_SYMBOL(sdw_find_row_index);
static int _sdw_program_slave_port_params(struct sdw_bus *bus,
struct sdw_slave *slave,
struct sdw_transport_params *t_params,
enum sdw_dpn_type type)
{
u32 addr1, addr2, addr3, addr4;
int ret;
u16 wbuf;
if (bus->params.next_bank) {
addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
} else {
addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
}
/* Program DPN_OffsetCtrl2 registers */
ret = sdw_write_no_pm(slave, addr1, t_params->offset2);
if (ret < 0) {
dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed\n");
return ret;
}
/* DP0 does not implement BlockCtrl3 */
if (t_params->port_num) {
/* Program DPN_BlockCtrl3 register */
ret = sdw_write_no_pm(slave, addr2, t_params->blk_pkg_mode);
if (ret < 0) {
dev_err(bus->dev, "DPN_BlockCtrl3 register write failed\n");
return ret;
}
}
/*
* Data ports are FULL, SIMPLE and REDUCED. This function handles
* FULL and REDUCED only and beyond this point only FULL is
* handled, so bail out if we are not FULL data port type
*/
if (type != SDW_DPN_FULL)
return ret;
/* Program DPN_SampleCtrl2 register */
wbuf = FIELD_GET(SDW_DPN_SAMPLECTRL_HIGH, t_params->sample_interval - 1);
ret = sdw_write_no_pm(slave, addr3, wbuf);
if (ret < 0) {
dev_err(bus->dev, "DPN_SampleCtrl2 register write failed\n");
return ret;
}
/* Program DPN_HCtrl register */
wbuf = FIELD_PREP(SDW_DPN_HCTRL_HSTART, t_params->hstart);
wbuf |= FIELD_PREP(SDW_DPN_HCTRL_HSTOP, t_params->hstop);
ret = sdw_write_no_pm(slave, addr4, wbuf);
if (ret < 0)
dev_err(bus->dev, "DPN_HCtrl register write failed\n");
return ret;
}
static int sdw_program_slave_port_params(struct sdw_bus *bus,
struct sdw_slave_runtime *s_rt,
struct sdw_port_runtime *p_rt)
{
struct sdw_transport_params *t_params = &p_rt->transport_params;
struct sdw_port_params *p_params = &p_rt->port_params;
struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
u32 addr1, addr2, addr3, addr4, addr5, addr6;
enum sdw_dpn_type port_type;
bool read_only_wordlength;
int ret;
u8 wbuf;
if (s_rt->slave->is_mockup_device)
return 0;
if (t_params->port_num) {
struct sdw_dpn_prop *dpn_prop;
dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave, s_rt->direction,
t_params->port_num);
if (!dpn_prop)
return -EINVAL;
read_only_wordlength = dpn_prop->read_only_wordlength;
port_type = dpn_prop->type;
} else {
read_only_wordlength = false;
port_type = SDW_DPN_FULL;
}
addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
if (bus->params.next_bank) {
addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
} else {
addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
}
/* Program DPN_PortCtrl register */
wbuf = FIELD_PREP(SDW_DPN_PORTCTRL_DATAMODE, p_params->data_mode);
wbuf |= FIELD_PREP(SDW_DPN_PORTCTRL_FLOWMODE, p_params->flow_mode);
ret = sdw_update_no_pm(s_rt->slave, addr1, 0xF, wbuf);
if (ret < 0) {
dev_err(&s_rt->slave->dev,
"DPN_PortCtrl register write failed for port %d\n",
t_params->port_num);
return ret;
}
if (!read_only_wordlength) {
/* Program DPN_BlockCtrl1 register */
ret = sdw_write_no_pm(s_rt->slave, addr2, (p_params->bps - 1));
if (ret < 0) {
dev_err(&s_rt->slave->dev,
"DPN_BlockCtrl1 register write failed for port %d\n",
t_params->port_num);
return ret;
}
}
/* Program DPN_SampleCtrl1 register */
wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
ret = sdw_write_no_pm(s_rt->slave, addr3, wbuf);
if (ret < 0) {
dev_err(&s_rt->slave->dev,
"DPN_SampleCtrl1 register write failed for port %d\n",
t_params->port_num);
return ret;
}
/* Program DPN_OffsetCtrl1 registers */
ret = sdw_write_no_pm(s_rt->slave, addr4, t_params->offset1);
if (ret < 0) {
dev_err(&s_rt->slave->dev,
"DPN_OffsetCtrl1 register write failed for port %d\n",
t_params->port_num);
return ret;
}
/* Program DPN_BlockCtrl2 register*/
if (t_params->blk_grp_ctrl_valid) {
ret = sdw_write_no_pm(s_rt->slave, addr5, t_params->blk_grp_ctrl);
if (ret < 0) {
dev_err(&s_rt->slave->dev,
"DPN_BlockCtrl2 reg write failed for port %d\n",
t_params->port_num);
return ret;
}
}
/* program DPN_LaneCtrl register */
if (slave_prop->lane_control_support) {
ret = sdw_write_no_pm(s_rt->slave, addr6, t_params->lane_ctrl);
if (ret < 0) {
dev_err(&s_rt->slave->dev,
"DPN_LaneCtrl register write failed for port %d\n",
t_params->port_num);
return ret;
}
}
if (port_type != SDW_DPN_SIMPLE) {
ret = _sdw_program_slave_port_params(bus, s_rt->slave,
t_params, port_type);
if (ret < 0)
dev_err(&s_rt->slave->dev,
"Transport reg write failed for port: %d\n",
t_params->port_num);
}
return ret;
}
static int sdw_program_master_port_params(struct sdw_bus *bus,
struct sdw_port_runtime *p_rt)
{
int ret;
/*
* we need to set transport and port parameters for the port.
* Transport parameters refers to the sample interval, offsets and
* hstart/stop etc of the data. Port parameters refers to word
* length, flow mode etc of the port
*/
ret = bus->port_ops->dpn_set_port_transport_params(bus,
&p_rt->transport_params,
bus->params.next_bank);
if (ret < 0)
return ret;
return bus->port_ops->dpn_set_port_params(bus,
&p_rt->port_params,
bus->params.next_bank);
}
/**
* sdw_program_port_params() - Programs transport parameters of Master(s)
* and Slave(s)
*
* @m_rt: Master stream runtime
*/
static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
{
struct sdw_slave_runtime *s_rt;
struct sdw_bus *bus = m_rt->bus;
struct sdw_port_runtime *p_rt;
int ret = 0;
/* Program transport & port parameters for Slave(s) */
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
if (ret < 0)
return ret;
}
}
/* Program transport & port parameters for Master(s) */
list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
ret = sdw_program_master_port_params(bus, p_rt);
if (ret < 0)
return ret;
}
return 0;
}
/**
* sdw_enable_disable_slave_ports: Enable/disable slave data port
*
* @bus: bus instance
* @s_rt: slave runtime
* @p_rt: port runtime
* @en: enable or disable operation
*
* This function only sets the enable/disable bits in the relevant bank, the
* actual enable/disable is done with a bank switch
*/
static int sdw_enable_disable_slave_ports(struct sdw_bus *bus,
struct sdw_slave_runtime *s_rt,
struct sdw_port_runtime *p_rt,
bool en)
{
struct sdw_transport_params *t_params = &p_rt->transport_params;
u32 addr;
int ret;
if (bus->params.next_bank)
addr = SDW_DPN_CHANNELEN_B1(p_rt->num);
else
addr = SDW_DPN_CHANNELEN_B0(p_rt->num);
/*
* Since bus doesn't support sharing a port across two streams,
* it is safe to reset this register
*/
if (en)
ret = sdw_write_no_pm(s_rt->slave, addr, p_rt->ch_mask);
else
ret = sdw_write_no_pm(s_rt->slave, addr, 0x0);
if (ret < 0)
dev_err(&s_rt->slave->dev,
"Slave chn_en reg write failed:%d port:%d\n",
ret, t_params->port_num);
return ret;
}
static int sdw_enable_disable_master_ports(struct sdw_master_runtime *m_rt,
struct sdw_port_runtime *p_rt,
bool en)
{
struct sdw_transport_params *t_params = &p_rt->transport_params;
struct sdw_bus *bus = m_rt->bus;
struct sdw_enable_ch enable_ch;
int ret;
enable_ch.port_num = p_rt->num;
enable_ch.ch_mask = p_rt->ch_mask;
enable_ch.enable = en;
/* Perform Master port channel(s) enable/disable */
if (bus->port_ops->dpn_port_enable_ch) {
ret = bus->port_ops->dpn_port_enable_ch(bus,
&enable_ch,
bus->params.next_bank);
if (ret < 0) {
dev_err(bus->dev,
"Master chn_en write failed:%d port:%d\n",
ret, t_params->port_num);
return ret;
}
} else {
dev_err(bus->dev,
"dpn_port_enable_ch not supported, %s failed\n",
str_enable_disable(en));
return -EINVAL;
}
return 0;
}
/**
* sdw_enable_disable_ports() - Enable/disable port(s) for Master and
* Slave(s)
*
* @m_rt: Master stream runtime
* @en: mode (enable/disable)
*/
static int sdw_enable_disable_ports(struct sdw_master_runtime *m_rt, bool en)
{
struct sdw_port_runtime *s_port, *m_port;
struct sdw_slave_runtime *s_rt;
int ret = 0;
/* Enable/Disable Slave port(s) */
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
list_for_each_entry(s_port, &s_rt->port_list, port_node) {
ret = sdw_enable_disable_slave_ports(m_rt->bus, s_rt,
s_port, en);
if (ret < 0)
return ret;
}
}
/* Enable/Disable Master port(s) */
list_for_each_entry(m_port, &m_rt->port_list, port_node) {
ret = sdw_enable_disable_master_ports(m_rt, m_port, en);
if (ret < 0)
return ret;
}
return 0;
}
static int sdw_do_port_prep(struct sdw_slave_runtime *s_rt,
struct sdw_prepare_ch prep_ch,
enum sdw_port_prep_ops cmd)
{
int ret = 0;
struct sdw_slave *slave = s_rt->slave;
mutex_lock(&slave->sdw_dev_lock);
if (slave->probed) {
struct device *dev = &slave->dev;
struct sdw_driver *drv = drv_to_sdw_driver(dev->driver);
if (drv->ops && drv->ops->port_prep) {
ret = drv->ops->port_prep(slave, &prep_ch, cmd);
if (ret < 0)
dev_err(dev, "Slave Port Prep cmd %d failed: %d\n",
cmd, ret);
}
}
mutex_unlock(&slave->sdw_dev_lock);
return ret;
}
static int sdw_prep_deprep_slave_ports(struct sdw_bus *bus,
struct sdw_slave_runtime *s_rt,
struct sdw_port_runtime *p_rt,
bool prep)
{
struct completion *port_ready;
struct sdw_dpn_prop *dpn_prop;
struct sdw_prepare_ch prep_ch;
u32 imp_def_interrupts;
bool simple_ch_prep_sm;
u32 ch_prep_timeout;
bool intr = false;
int ret = 0, val;
u32 addr;
prep_ch.num = p_rt->num;
prep_ch.ch_mask = p_rt->ch_mask;
if (p_rt->num) {
dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave, s_rt->direction, prep_ch.num);
if (!dpn_prop) {
dev_err(bus->dev,
"Slave Port:%d properties not found\n", prep_ch.num);
return -EINVAL;
}
imp_def_interrupts = dpn_prop->imp_def_interrupts;
simple_ch_prep_sm = dpn_prop->simple_ch_prep_sm;
ch_prep_timeout = dpn_prop->ch_prep_timeout;
} else {
struct sdw_dp0_prop *dp0_prop = s_rt->slave->prop.dp0_prop;
if (!dp0_prop) {
dev_err(bus->dev,
"Slave DP0 properties not found\n");
return -EINVAL;
}
imp_def_interrupts = dp0_prop->imp_def_interrupts;
simple_ch_prep_sm = dp0_prop->simple_ch_prep_sm;
ch_prep_timeout = dp0_prop->ch_prep_timeout;
}
prep_ch.prepare = prep;
prep_ch.bank = bus->params.next_bank;
if (imp_def_interrupts || !simple_ch_prep_sm ||
bus->params.s_data_mode != SDW_PORT_DATA_MODE_NORMAL)
intr = true;
/*
* Enable interrupt before Port prepare.
* For Port de-prepare, it is assumed that port
* was prepared earlier
*/
if (prep && intr) {
ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
imp_def_interrupts);
if (ret < 0)
return ret;
}
/* Inform slave about the impending port prepare */
sdw_do_port_prep(s_rt, prep_ch, prep ? SDW_OPS_PORT_PRE_PREP : SDW_OPS_PORT_PRE_DEPREP);
/* Prepare Slave port implementing CP_SM */
if (!simple_ch_prep_sm) {
addr = SDW_DPN_PREPARECTRL(p_rt->num);
if (prep)
ret = sdw_write_no_pm(s_rt->slave, addr, p_rt->ch_mask);
else
ret = sdw_write_no_pm(s_rt->slave, addr, 0x0);
if (ret < 0) {
dev_err(&s_rt->slave->dev,
"Slave prep_ctrl reg write failed\n");
return ret;
}
/* Wait for completion on port ready */
port_ready = &s_rt->slave->port_ready[prep_ch.num];
wait_for_completion_timeout(port_ready,
msecs_to_jiffies(ch_prep_timeout));
val = sdw_read_no_pm(s_rt->slave, SDW_DPN_PREPARESTATUS(p_rt->num));
if ((val < 0) || (val & p_rt->ch_mask)) {
ret = (val < 0) ? val : -ETIMEDOUT;
dev_err(&s_rt->slave->dev,
"Chn prep failed for port %d: %d\n", prep_ch.num, ret);
return ret;
}
}
/* Inform slaves about ports prepared */
sdw_do_port_prep(s_rt, prep_ch, prep ? SDW_OPS_PORT_POST_PREP : SDW_OPS_PORT_POST_DEPREP);
/* Disable interrupt after Port de-prepare */
if (!prep && intr)
ret = sdw_configure_dpn_intr(s_rt->slave, p_rt->num, prep,
imp_def_interrupts);
return ret;
}
static int sdw_prep_deprep_master_ports(struct sdw_master_runtime *m_rt,
struct sdw_port_runtime *p_rt,
bool prep)
{
struct sdw_transport_params *t_params = &p_rt->transport_params;
struct sdw_bus *bus = m_rt->bus;
const struct sdw_master_port_ops *ops = bus->port_ops;
struct sdw_prepare_ch prep_ch;
int ret = 0;
prep_ch.num = p_rt->num;
prep_ch.ch_mask = p_rt->ch_mask;
prep_ch.prepare = prep; /* Prepare/De-prepare */
prep_ch.bank = bus->params.next_bank;
/* Pre-prepare/Pre-deprepare port(s) */
if (ops->dpn_port_prep) {
ret = ops->dpn_port_prep(bus, &prep_ch);
if (ret < 0) {
dev_err(bus->dev, "Port prepare failed for port:%d\n",
t_params->port_num);
return ret;
}
}
return ret;
}
/**
* sdw_prep_deprep_ports() - Prepare/De-prepare port(s) for Master(s) and
* Slave(s)
*
* @m_rt: Master runtime handle
* @prep: Prepare or De-prepare
*/
static int sdw_prep_deprep_ports(struct sdw_master_runtime *m_rt, bool prep)
{
struct sdw_slave_runtime *s_rt;
struct sdw_port_runtime *p_rt;
int ret = 0;
/* Prepare/De-prepare Slave port(s) */
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
ret = sdw_prep_deprep_slave_ports(m_rt->bus, s_rt,
p_rt, prep);
if (ret < 0)
return ret;
}
}
/* Prepare/De-prepare Master port(s) */
list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
ret = sdw_prep_deprep_master_ports(m_rt, p_rt, prep);
if (ret < 0)
return ret;
}
return ret;
}
/**
* sdw_notify_config() - Notify bus configuration
*
* @m_rt: Master runtime handle
*
* This function notifies the Master(s) and Slave(s) of the
* new bus configuration.
*/
static int sdw_notify_config(struct sdw_master_runtime *m_rt)
{
struct sdw_slave_runtime *s_rt;
struct sdw_bus *bus = m_rt->bus;
struct sdw_slave *slave;
int ret;
if (bus->ops->set_bus_conf) {
ret = bus->ops->set_bus_conf(bus, &bus->params);
if (ret < 0)
return ret;
}
list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
slave = s_rt->slave;
mutex_lock(&slave->sdw_dev_lock);
if (slave->probed) {
struct device *dev = &slave->dev;
struct sdw_driver *drv = drv_to_sdw_driver(dev->driver);
if (drv->ops && drv->ops->bus_config) {
ret = drv->ops->bus_config(slave, &bus->params);
if (ret < 0) {
dev_err(dev, "Notify Slave: %d failed\n",
slave->dev_num);
mutex_unlock(&slave->sdw_dev_lock);
return ret;
}
}
}
mutex_unlock(&slave->sdw_dev_lock);
}
return 0;
}
/**
* sdw_program_params() - Program transport and port parameters for Master(s)
* and Slave(s)
*
* @bus: SDW bus instance
* @prepare: true if sdw_program_params() is called by _prepare.
*/
static int sdw_program_params(struct sdw_bus *bus, bool prepare)
{
struct sdw_master_runtime *m_rt;
struct sdw_slave *slave;
int ret = 0;
u32 addr1;
/* Check if all Peripherals comply with SDCA */
list_for_each_entry(slave, &bus->slaves, node) {
if (!slave->dev_num_sticky)
continue;
if (!is_clock_scaling_supported_by_slave(slave)) {
dev_dbg(&slave->dev, "The Peripheral doesn't comply with SDCA\n");
goto manager_runtime;
}
}
if (bus->params.next_bank)
addr1 = SDW_SCP_BUSCLOCK_SCALE_B1;
else
addr1 = SDW_SCP_BUSCLOCK_SCALE_B0;
/* Program SDW_SCP_BUSCLOCK_SCALE if all Peripherals comply with SDCA */
list_for_each_entry(slave, &bus->slaves, node) {
int scale_index;
u8 base;
if (!slave->dev_num_sticky)
continue;
scale_index = sdw_slave_get_scale_index(slave, &base);
if (scale_index < 0)
return scale_index;
ret = sdw_write_no_pm(slave, addr1, scale_index);
if (ret < 0) {
dev_err(&slave->dev, "SDW_SCP_BUSCLOCK_SCALE register write failed\n");
return ret;
}
}
manager_runtime:
list_for_each_entry(m_rt, &bus->m_rt_list, bus_node) {
/*
* this loop walks through all master runtimes for a
* bus, but the ports can only be configured while
* explicitly preparing a stream or handling an
* already-prepared stream otherwise.
*/
if (!prepare &&
m_rt->stream->state == SDW_STREAM_CONFIGURED)
continue;
ret = sdw_program_port_params(m_rt);
if (ret < 0) {
dev_err(bus->dev,
"Program transport params failed: %d\n", ret);
return ret;
}
ret = sdw_notify_config(m_rt);
if (ret < 0) {
dev_err(bus->dev,
"Notify bus config failed: %d\n", ret);
return ret;
}
/* Enable port(s) on alternate bank for all active streams */
if (m_rt->stream->state != SDW_STREAM_ENABLED)
continue;
ret = sdw_enable_disable_ports(m_rt, true);
if (ret < 0) {
dev_err(bus->dev, "Enable channel failed: %d\n", ret);
return ret;
}
}
return ret;
}
static int sdw_bank_switch(struct sdw_bus *bus, int m_rt_count)
{
int col_index, row_index;
bool multi_link;
struct sdw_msg *wr_msg;
u8 *wbuf;
int ret;
u16 addr;
wr_msg = kzalloc(sizeof(*wr_msg), GFP_KERNEL);
if (!wr_msg)
return -ENOMEM;
wbuf = kzalloc(sizeof(*wbuf), GFP_KERNEL);
if (!wbuf) {
ret = -ENOMEM;
goto error_1;
}
/* Get row and column index to program register */
col_index = sdw_find_col_index(bus->params.col);
row_index = sdw_find_row_index(bus->params.row);
wbuf[0] = col_index | (row_index << 3);
if (bus->params.next_bank)
addr = SDW_SCP_FRAMECTRL_B1;
else
addr = SDW_SCP_FRAMECTRL_B0;
sdw_fill_msg(wr_msg, NULL, addr, 1, SDW_BROADCAST_DEV_NUM,
SDW_MSG_FLAG_WRITE, wbuf);
wr_msg->ssp_sync = true;
/*
* Set the multi_link flag only when both the hardware supports
* and hardware-based sync is required
*/
multi_link = bus->multi_link && (m_rt_count >= bus->hw_sync_min_links);
if (multi_link)
ret = sdw_transfer_defer(bus, wr_msg);
else
ret = sdw_transfer(bus, wr_msg);
if (ret < 0 && ret != -ENODATA) {
dev_err(bus->dev, "Slave frame_ctrl reg write failed\n");
goto error;
}
if (!multi_link) {
kfree(wbuf);
kfree(wr_msg);
bus->defer_msg.msg = NULL;
bus->params.curr_bank = !bus->params.curr_bank;
bus->params.next_bank = !bus->params.next_bank;
}
return 0;
error:
kfree(wbuf);
error_1:
kfree(wr_msg);
bus->defer_msg.msg = NULL;
return ret;
}
/**
* sdw_ml_sync_bank_switch: Multilink register bank switch
*
* @bus: SDW bus instance
* @multi_link: whether this is a multi-link stream with hardware-based sync
*
* Caller function should free the buffers on error
*/
static int sdw_ml_sync_bank_switch(struct sdw_bus *bus, bool multi_link)
{
unsigned long time_left;
if (!multi_link)
return 0;
/* Wait for completion of transfer */
time_left = wait_for_completion_timeout(&bus->defer_msg.complete,
bus->bank_switch_timeout);
if (!time_left) {
dev_err(bus->dev, "Controller Timed out on bank switch\n");
return -ETIMEDOUT;
}
bus->params.curr_bank = !bus->params.curr_bank;
bus->params.next_bank = !bus->params.next_bank;
if (bus->defer_msg.msg) {
kfree(bus->defer_msg.msg->buf);
kfree(bus->defer_msg.msg);
bus->defer_msg.msg = NULL;
}
return 0;
}
static int do_bank_switch(struct sdw_stream_runtime *stream)
{
struct sdw_master_runtime *m_rt;
const struct sdw_master_ops *ops;
struct sdw_bus *bus;
bool multi_link = false;
int m_rt_count;
int ret = 0;
m_rt_count = stream->m_rt_count;
list_for_each_entry(m_rt, &stream->master_list, stream_node) {
bus = m_rt->bus;
ops = bus->ops;
if (bus->multi_link && m_rt_count >= bus->hw_sync_min_links) {
multi_link = true;
mutex_lock(&bus->msg_lock);
}
/* Pre-bank switch */
if (ops->pre_bank_switch) {
ret = ops->pre_bank_switch(bus);
if (ret < 0) {
dev_err(bus->dev,
"Pre bank switch op failed: %d\n", ret);
goto msg_unlock;
}
}
/*
* Perform Bank switch operation.
* For multi link cases, the actual bank switch is
* synchronized across all Masters and happens later as a
* part of post_bank_switch ops.
*/
ret = sdw_bank_switch(bus, m_rt_count);
if (ret < 0) {
dev_err(bus->dev, "Bank switch failed: %d\n", ret);
goto error;
}
}
/*
* For multi link cases, it is expected that the bank switch is
* triggered by the post_bank_switch for the first Master in the list
* and for the other Masters the post_bank_switch() should return doing
* nothing.
*/
list_for_each_entry(m_rt, &stream->master_list, stream_node) {
bus = m_rt->bus;
ops = bus->ops;
/* Post-bank switch */
if (ops->post_bank_switch) {
ret = ops->post_bank_switch(bus);
if (ret < 0) {
dev_err(bus->dev,
"Post bank switch op failed: %d\n",
ret);
goto error;
}
} else if (multi_link) {
dev_err(bus->dev,
"Post bank switch ops not implemented\n");
ret = -EINVAL;
goto error;
}
/* Set the bank switch timeout to default, if not set */
if (!bus->bank_switch_timeout)
bus->bank_switch_timeout = DEFAULT_BANK_SWITCH_TIMEOUT;
/* Check if bank switch was successful */
ret = sdw_ml_sync_bank_switch(bus, multi_link);
if (ret < 0) {
dev_err(bus->dev,
"multi link bank switch failed: %d\n", ret);
goto error;
}
if (multi_link)
mutex_unlock(&bus->msg_lock);
}
return ret;
error:
list_for_each_entry(m_rt, &stream->master_list, stream_node) {
bus = m_rt->bus;
if (bus->defer_msg.msg) {
kfree(bus->defer_msg.msg->buf);
kfree(bus->defer_msg.msg);
bus->defer_msg.msg = NULL;
}
}
msg_unlock:
if (multi_link) {
list_for_each_entry(m_rt, &stream->master_list, stream_node) {
bus = m_rt->bus;
if (mutex_is_locked(&bus->msg_lock))
mutex_unlock(&bus->msg_lock);
}
}
return ret;
}
static struct sdw_port_runtime *sdw_port_alloc(struct list_head *port_list)
{
struct sdw_port_runtime *p_rt;
p_rt = kzalloc(sizeof(*p_rt), GFP_KERNEL);
if (!p_rt)
return NULL;
list_add_tail(&p_rt->port_node, port_list);
return p_rt;
}
static int sdw_port_config(struct sdw_port_runtime *p_rt,
const struct sdw_port_config *port_config,
int port_index)
{
p_rt->ch_mask = port_config[port_index].ch_mask;
p_rt->num = port_config[port_index].num;
/*
* TODO: Check port capabilities for requested configuration
*/
return 0;
}
static void sdw_port_free(struct sdw_port_runtime *p_rt)
{
list_del(&p_rt->port_node);
kfree(p_rt);
}
static bool sdw_slave_port_allocated(struct sdw_slave_runtime *s_rt)
{
return !list_empty(&s_rt->port_list);
}