Merge pull request #4118 from ashnaaseth2325-oss/fix/jpeg-rle-ddstrb-reset

jpeg_rle: Add missing reset to ddstrb pipeline register to prevent spurious go after reset

Author: maliberty

flow/designs/sky130hd/jpeg/rules-base.json

@@ -32,7 +32,7 @@
         "compare": ">="
     },
     "cts__timing__setup__tns": {
-        "value": -155.0,
+        "value": -170.0,
         "compare": ">="
     },
     "cts__timing__hold__ws": {
@@ -44,15 +44,15 @@
         "compare": ">="
     },
     "globalroute__antenna_diodes_count": {
-        "value": 100,
+        "value": 115,
         "compare": "<="
     },
     "globalroute__timing__setup__ws": {
-        "value": -0.899,
+        "value": -1.16,
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -201.0,
+        "value": -268.0,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -80,11 +80,11 @@
         "compare": "<="
     },
     "finish__timing__setup__ws": {
-        "value": -0.603,
+        "value": -0.943,
         "compare": ">="
     },
     "finish__timing__setup__tns": {
-        "value": -96.0,
+        "value": -146.0,
         "compare": ">="
     },
     "finish__timing__hold__ws": {

flow/designs/sky130hs/jpeg/rules-base.json

@@ -12,19 +12,19 @@
         "compare": "<="
     },
     "placeopt__design__instance__count__stdcell": {
-        "value": 56019,
+        "value": 55868,
         "compare": "<="
     },
     "detailedplace__design__violations": {
         "value": 0,
         "compare": "=="
     },
     "cts__design__instance__count__setup_buffer": {
-        "value": 4871,
+        "value": 4858,
         "compare": "<="
     },
     "cts__design__instance__count__hold_buffer": {
-        "value": 4871,
+        "value": 4858,
         "compare": "<="
     },
     "cts__timing__setup__ws": {
@@ -52,7 +52,7 @@
         "compare": ">="
     },
     "globalroute__timing__setup__tns": {
-        "value": -0.809,
+        "value": -1.92,
         "compare": ">="
     },
     "globalroute__timing__hold__ws": {
@@ -76,7 +76,7 @@
         "compare": "<="
     },
     "detailedroute__antenna_diodes_count": {
-        "value": 100,
+        "value": 102,
         "compare": "<="
     },
     "finish__timing__setup__ws": {

flow/designs/src/jpeg/jpeg_rle.v

@@ -98,8 +98,11 @@ module jpeg_rle(clk, rst, ena, dstrb, din, size, rlen, amp, douten, bstart);
 	//
 
 	reg ddstrb;
-	always @(posedge clk)
-	  ddstrb <= #1 dstrb;
+	always @(posedge clk or negedge rst)
+	  if (!rst)
+	    ddstrb <= #1 1'b0;
+	  else
+	    ddstrb <= #1 dstrb;
 
 	// generate run-length encoded signals
 	jpeg_rle1 rle(