rtl: fix missing reset on wden_p in WDT32

wden_p lacked an async reset, causing a simulation/synthesis
mismatch: WDOV could be driven X in simulation immediately
after reset deassertion when WDEN is asserted.

Signed-off-by: Ashnaa Seth <[email protected]>
Signed-off-by: ashnaaseth2325-oss <[email protected]>

Author: ashnaaseth2325-oss

flow/designs/src/chameleon/IPs/WDT32.v

@@ -40,8 +40,9 @@ module WDT32 (
 	end
 
 	reg wden_p;
-	always @(posedge clk) 
-	  wden_p <= WDEN;
+	always @(posedge clk or posedge rst)
+	  if (rst) wden_p <= 1'b0;
+	  else     wden_p <= WDEN;
 
 	always @(posedge clk or posedge rst)
 	begin