bazel: fix BUILD files for analysis of all designs

- Add exports_files(glob(["platforms/**"])) to flow/BUILD.bazel for
  ADDITIONAL_LEFS/LIBS from PLATFORM_DIR
- Add :verilog filegroups to chameleon, cva6, microwatt subdirs
- Add :include filegroups for VERILOG_INCLUDE_DIRS targets
- Add :lef/:lib/:gds filegroups for design-local macro files
- Add .cfg and .sv extensions to platform PDK globs
- Add BUILD.bazel for riscv32i-mock-sram/fakeram7_256x32 sub-design
- Add BUILD.bazel for src/mock-array (needed by mock-cpu)

All 701 targets pass analysis, builds are running.

Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Signed-off-by: Øyvind Harboe <oyvind.harboe@zylin.com>

Author: oharboe

flow/BUILD.bazel

@@ -1,5 +1,12 @@
 load("@bazel-orfs//:openroad.bzl", "orfs_pdk")
 
+# Export platform files so designs can reference them directly via
+# ADDITIONAL_LEFS, ADDITIONAL_LIBS, etc. from PLATFORM_DIR.
+exports_files(
+    glob(["platforms/**"]),
+    visibility = ["//visibility:public"],
+)
+
 # files shared between scripts/synth.sh and scripts/flow.sh steps
 MAKEFILE_SHARED = [
     "scripts/*.py",
@@ -45,10 +52,10 @@ filegroup(
             pdk = pdk,
         )
         for ext in {
-            "asap7": ["gds", "lef", "lib", "lib.gz", "lyt", "mk", "rules", "sdc", "tcl", "v"],
-            "gf180": ["gds", "lef", "lib.gz", "lyt", "mk", "rules", "tcl", "v"],
+            "asap7": ["cfg", "gds", "lef", "lib", "lib.gz", "lyt", "mk", "rules", "sdc", "sv", "tcl", "v"],
+            "gf180": ["cfg", "gds", "lef", "lib.gz", "lyt", "mk", "rules", "tcl", "v"],
             "ihp-sg13g2": ["gds", "json", "lef", "lib", "lyt", "mk", "rules", "tcl", "v"],
-            "nangate45": ["gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "v"],
+            "nangate45": ["cfg", "gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "v"],
             "sky130hd": ["gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "tlef", "v"],
             "sky130hs": ["gds", "lef", "lib", "lyt", "mk", "rules", "tcl", "tlef", "v"],
         }[pdk]

flow/designs/asap7/riscv32i-mock-sram/fakeram7_256x32/BUILD.bazel

@@ -0,0 +1,6 @@
+load("@bazel-orfs//:openroad.bzl", "orfs_design")
+load("@orfs_designs//:designs.bzl", "DESIGNS")
+
+exports_files(glob(["*"]))
+
+orfs_design(designs = DESIGNS)

flow/designs/asap7/swerv_wrapper/lef/BUILD.bazel

@@ -0,0 +1,10 @@
+exports_files(
+    glob(["*"]),
+    visibility = ["//visibility:public"],
+)
+
+filegroup(
+    name = "lef",
+    srcs = glob(["*"]),
+    visibility = ["//visibility:public"],
+)

flow/designs/asap7/swerv_wrapper/lib/BUILD.bazel

@@ -0,0 +1,10 @@
+exports_files(
+    glob(["*"]),
+    visibility = ["//visibility:public"],
+)
+
+filegroup(
+    name = "lib",
+    srcs = glob(["*"]),
+    visibility = ["//visibility:public"],
+)

flow/designs/sky130hd/chameleon/gds/BUILD.bazel

@@ -0,0 +1,10 @@
+exports_files(
+    glob(["*"]),
+    visibility = ["//visibility:public"],
+)
+
+filegroup(
+    name = "gds",
+    srcs = glob(["*"]),
+    visibility = ["//visibility:public"],
+)

flow/designs/sky130hd/chameleon/lef/BUILD.bazel

@@ -0,0 +1,10 @@
+exports_files(
+    glob(["*"]),
+    visibility = ["//visibility:public"],
+)
+
+filegroup(
+    name = "lef",
+    srcs = glob(["*"]),
+    visibility = ["//visibility:public"],
+)

flow/designs/sky130hd/microwatt/gds/BUILD.bazel

@@ -0,0 +1,10 @@
+exports_files(
+    glob(["*"]),
+    visibility = ["//visibility:public"],
+)
+
+filegroup(
+    name = "gds",
+    srcs = glob(["*"]),
+    visibility = ["//visibility:public"],
+)

flow/designs/sky130hd/microwatt/lef/BUILD.bazel

@@ -0,0 +1,10 @@
+exports_files(
+    glob(["*"]),
+    visibility = ["//visibility:public"],
+)
+
+filegroup(
+    name = "lef",
+    srcs = glob(["*"]),
+    visibility = ["//visibility:public"],
+)

flow/designs/sky130hd/microwatt/lib/BUILD.bazel

@@ -0,0 +1,10 @@
+exports_files(
+    glob(["*"]),
+    visibility = ["//visibility:public"],
+)
+
+filegroup(
+    name = "lib",
+    srcs = glob(["*"]),
+    visibility = ["//visibility:public"],
+)

flow/designs/src/chameleon/AHB_sys_0/APB_sys_0/BUILD.bazel

@@ -2,3 +2,9 @@ exports_files(
     glob(["*.v", "*.sv"], allow_empty = True),
     visibility = ["//visibility:public"],
 )
+
+filegroup(
+    name = "verilog",
+    srcs = glob(include = ["*.v", "*.sv"], allow_empty = True),
+    visibility = ["//visibility:public"],
+)