bazel: enable 12 previously-blocked designs

Enable orfs_design() for designs that were blocked on bazel-orfs
parser improvements. The bazel-orfs parser now correctly resolves
$(DESIGN_NAME), $(DESIGN_NICKNAME), $(PLATFORM_DIR), and explicit
file paths in VERILOG_FILES. Block sub-packages (uart_rx,
I2cDeviceCtrl) get BUILD.bazel files for file exports.

Newly enabled designs (need metric threshold tuning):
- asap7: mock-alu
- gf180: uart-blocks (with uart_rx block)
- ihp-sg13g2: i2c-gpio-expander (with I2cDeviceCtrl block)
- nangate45: ariane133, ariane136, black_parrot, bp_be_top,
  bp_fe_top, bp_multi_top, bp_quad, mempool_group, swerv_wrapper

Co-Authored-By: Claude Opus 4.6 (1M context) <[email protected]>
Signed-off-by: Øyvind Harboe <[email protected]>

Author: oharboe

bazel-orfs.md

@@ -4,8 +4,9 @@ This is an early integration of [bazel-orfs](https://github.com/The-OpenROAD-Pro
 into OpenROAD-flow-scripts. It lets you build ORFS designs with Bazel
 using the same `config.mk` files you already have.
 
-**Status**: beta -- 46 designs across 6 public PDK platforms build and
-pass QoR tests. Platforms without public PDK files (gf12, gf55,
+**Status**: beta -- 58 designs across 6 public PDK platforms have
+`orfs_design()` enabled. 46 pass QoR tests; 12 newly enabled designs
+need metric thresholds. Platforms without public PDK files (gf12, gf55,
 rapidus2hp) are not wired up.
 
 ## Quick Start
@@ -50,12 +51,13 @@ Each enabled design gets these targets automatically from its `config.mk`:
 Each stage depends on the previous one, so building `_final` runs the
 entire flow.
 
-## Working Designs (46 passing tests)
+## Working Designs (46 passing tests + 12 newly enabled)
 
-All designs below have `orfs_design()` enabled and pass
-`bazelisk test` with QoR regression checks.
+All designs below have `orfs_design()` enabled. Designs marked
+**(new)** were recently unblocked and need metric threshold tuning
+before `bazelisk test` passes.
 
-### asap7 (16 designs)
+### asap7 (17 designs)
 
 | Design | DESIGN_NAME | Notes |
 |--------|-------------|-------|
@@ -75,6 +77,7 @@ All designs below have `orfs_design()` enabled and pass
 | `mock-cpu` | mock_cpu | mock CPU with FIFO |
 | `swerv_wrapper` | swerv_wrapper | SweRV EH1 |
 | `cva6` | cva6 | CVA6 RISC-V (~63 min) |
+| `mock-alu` | MockAlu | **(new)** mock ALU |
 
 ### sky130hd (7 designs)
 
@@ -88,7 +91,7 @@ All designs below have `orfs_design()` enabled and pass
 | `chameleon` | soc_core | SoC with macros |
 | `microwatt` | microwatt | POWER ISA core |
 
-### nangate45 (7 designs)
+### nangate45 (16 designs)
 
 | Design | DESIGN_NAME | Notes |
 |--------|-------------|-------|
@@ -99,8 +102,17 @@ All designs below have `orfs_design()` enabled and pass
 | `dynamic_node` | dynamic_node_top_wrap | NoC router |
 | `swerv` | swerv | SweRV EH1 |
 | `tinyRocket` | RocketTile | RISC-V Rocket |
-
-### gf180 (5 designs)
+| `ariane133` | ariane | **(new)** hierarchical |
+| `ariane136` | ariane | **(new)** hierarchical |
+| `black_parrot` | black_parrot | **(new)** hierarchical |
+| `bp_be_top` | bp_be_top | **(new)** BP back-end |
+| `bp_fe_top` | bp_fe_top | **(new)** BP front-end |
+| `bp_multi_top` | bp_multi_top | **(new)** BP multi-core |
+| `bp_quad` | black_parrot | **(new)** BP quad-core |
+| `mempool_group` | mempool_group | **(new)** MemPool group |
+| `swerv_wrapper` | swerv_wrapper | **(new)** SweRV wrapped |
+
+### gf180 (6 designs)
 
 | Design | DESIGN_NAME | Notes |
 |--------|-------------|-------|
@@ -109,8 +121,9 @@ All designs below have `orfs_design()` enabled and pass
 | `ibex` | ibex_core | RISC-V core |
 | `jpeg` | jpeg_encoder | JPEG encoder |
 | `riscv32i` | riscv | RISC-V RV32I |
+| `uart-blocks` | uart | **(new)** hierarchical with uart_rx block |
 
-### ihp-sg13g2 (6 designs)
+### ihp-sg13g2 (7 designs)
 
 | Design | DESIGN_NAME | Notes |
 |--------|-------------|-------|
@@ -120,6 +133,7 @@ All designs below have `orfs_design()` enabled and pass
 | `jpeg` | jpeg_encoder | JPEG encoder |
 | `riscv32i` | riscv | RISC-V RV32I |
 | `spi` | spi | SPI controller |
+| `i2c-gpio-expander` | I2cGpioExpanderTop | **(new)** I2C GPIO with I/O pads |
 
 ### sky130hs (5 designs)
 
@@ -131,62 +145,7 @@ All designs below have `orfs_design()` enabled and pass
 | `jpeg` | jpeg_encoder | JPEG encoder |
 | `riscv32i` | riscv | RISC-V RV32I |
 
-## Designs Blocked on bazel-orfs Changes
-
-These designs have BUILD.bazel with a commented-out `orfs_design()`
-and a `TODO(bazel-orfs)` note. They need changes in bazel-orfs before
-they can be enabled.
-
-### Hierarchical sub-design targets (riscv32i-mock-sram)
-
-`asap7/riscv32i-mock-sram` uses `include designs/asap7/riscv32i/config.mk`
-in its config.mk and has a `fakeram7_256x32/` sub-design directory.
-The `orfs_designs` rule generates spurious `riscv_top_*` targets in
-the sub-design package from the parent config. This causes a build
-failure because the sub-design lacks the parent's `rules-base.json`.
-
-**Fix**: `orfs_designs` should only generate targets from config.mk
-files that are directly in the scanned directory, not from included
-configs resolved at Make-time.
-
-### Specific file references in VERILOG_FILES
-
-Several designs list individual files in `VERILOG_FILES` from directories
-other than the design's own `src/` tree (e.g. `$(DESIGN_HOME)/src/ariane133/ariane.sv2v.v`
-or `$(DESIGN_HOME)/src/$(DESIGN_NAME)/pickled.v`). The `orfs_designs`
-rule resolves `$(wildcard ...)` patterns but does not handle explicit
-file paths that use `$(DESIGN_NAME)` or `$(DESIGN_NICKNAME)`.
-
-**Affected**: nangate45: ariane133, ariane136, black_parrot, bp_be_top,
-bp_fe_top, bp_multi_top, bp_quad, mempool_group, swerv_wrapper.
-
-**Fix**: Extend the `orfs_designs` config.mk parser to resolve
-`$(DESIGN_NAME)` and `$(DESIGN_NICKNAME)` variable references in
-explicit file paths, not just in `$(wildcard ...)` patterns.
-
-### VERILOG_FILES from non-matching src directory
-
-`gf180/uart-blocks` references `src/uart-no-param/*.v` -- a different
-src directory than its own name.
-
-**Fix**: The parser already handles `$(DESIGN_NICKNAME)` in wildcard
-patterns; verify it also resolves when the source directory name
-differs from the design directory name.
-
-### Platform-local verilog in VERILOG_FILES
-
-`ihp-sg13g2/i2c-gpio-expander` adds `$(PLATFORM_DIR)/verilog/sg13g2_io.v`
-to VERILOG_FILES and also references verilog from its own platform
-design directory (`$(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/*.v`).
-
-**Fix**: Support `$(PLATFORM_DIR)/...` file references in VERILOG_FILES
-by resolving them against the PDK target.
-
-### Generated verilog (mock-alu)
-
-`asap7/mock-alu` generates its verilog via `src/mock-alu/generate_*.py`
-scripts. Needs a Bazel `genrule` to run the Python generator before
-synthesis.
+## Designs Not Supported
 
 ### No VERILOG_FILES (minimal)
 
@@ -317,7 +276,6 @@ where reviews stall.
   `MODULE.bazel`.
 - Platforms without public PDK files (gf12, gf55, rapidus2hp) are not
   supported.
-- Some designs are blocked on bazel-orfs parser improvements (see above).
-- `riscv32i-mock-sram` hierarchical flow does not work yet.
+- 12 newly enabled designs need metric threshold tuning (`rules-base.json`).
 - This is a beta -- expect rough edges. File issues at
   https://github.com/The-OpenROAD-Project/bazel-orfs/issues

flow/designs/asap7/mock-alu/BUILD.bazel

@@ -3,6 +3,4 @@ load("@orfs_designs//:designs.bzl", "DESIGNS")
 
 exports_files(glob(["*"]))
 
-# TODO(bazel-orfs): orfs_design(designs = DESIGNS)
-# Blocked: verilog is generated by src/mock-alu/generate_*.py scripts,
-# not static files. Needs a genrule to produce the .v before synthesis.
+orfs_design(designs = DESIGNS)

flow/designs/gf180/uart-blocks/BUILD.bazel

@@ -3,5 +3,4 @@ load("@orfs_designs//:designs.bzl", "DESIGNS")
 
 exports_files(glob(["*"]))
 
-# TODO(bazel-orfs): orfs_design(designs = DESIGNS)
-# Blocked: config.mk references src/uart-no-param/*.v (different src dir than design name).
+orfs_design(designs = DESIGNS)

flow/designs/gf180/uart-blocks/uart_rx/BUILD.bazel

@@ -0,0 +1,6 @@
+load("@bazel-orfs//:openroad.bzl", "orfs_design")
+load("@orfs_designs//:designs.bzl", "DESIGNS")
+
+exports_files(glob(["*"]))
+
+orfs_design(designs = DESIGNS)

flow/designs/ihp-sg13g2/i2c-gpio-expander/BUILD.bazel

@@ -3,5 +3,4 @@ load("@orfs_designs//:designs.bzl", "DESIGNS")
 
 exports_files(glob(["*"]))
 
-# TODO(bazel-orfs): orfs_design(designs = DESIGNS)
-# Blocked: config.mk references $(PLATFORM_DIR)/verilog/sg13g2_io.v and design-local verilog.
+orfs_design(designs = DESIGNS)

flow/designs/ihp-sg13g2/i2c-gpio-expander/I2cDeviceCtrl/BUILD.bazel

@@ -0,0 +1,6 @@
+load("@bazel-orfs//:openroad.bzl", "orfs_design")
+load("@orfs_designs//:designs.bzl", "DESIGNS")
+
+exports_files(glob(["*"]))
+
+orfs_design(designs = DESIGNS)

flow/designs/nangate45/ariane133/BUILD.bazel

@@ -3,5 +3,4 @@ load("@orfs_designs//:designs.bzl", "DESIGNS")
 
 exports_files(glob(["*"]))
 
-# TODO(bazel-orfs): orfs_design(designs = DESIGNS)
-# Blocked: config.mk references specific file from src/ariane133/.
+orfs_design(designs = DESIGNS)

flow/designs/nangate45/ariane136/BUILD.bazel

@@ -3,5 +3,4 @@ load("@orfs_designs//:designs.bzl", "DESIGNS")
 
 exports_files(glob(["*"]))
 
-# TODO(bazel-orfs): orfs_design(designs = DESIGNS)
-# Blocked: config.mk references specific file from src/ariane136/.
+orfs_design(designs = DESIGNS)

flow/designs/nangate45/black_parrot/BUILD.bazel

@@ -3,5 +3,4 @@ load("@orfs_designs//:designs.bzl", "DESIGNS")
 
 exports_files(glob(["*"]))
 
-# TODO(bazel-orfs): orfs_design(designs = DESIGNS)
-# Blocked: config.mk references src/$(DESIGN_NAME)/pickled.v specific file.
+orfs_design(designs = DESIGNS)

flow/designs/nangate45/bp_be_top/BUILD.bazel

@@ -3,5 +3,4 @@ load("@orfs_designs//:designs.bzl", "DESIGNS")
 
 exports_files(glob(["*"]))
 
-# TODO(bazel-orfs): orfs_design(designs = DESIGNS)
-# Blocked: config.mk references src/$(DESIGN_NAME)/pickled.v specific file.
+orfs_design(designs = DESIGNS)