GitHub - freecores/embedded_risc: Embedded 32-bit RISC uProcessor with SDRAM Controller · GitHub

Name		Name	Last commit message	Last commit date
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Test_Bench_Verilog		Test_Bench_Verilog
Verilog		Verilog
SOC_Design.pdf		SOC_Design.pdf

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Embedded 32-bit RISC uProcessor with SDRAM Controller

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