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Pull requests: llvm/circt

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238 Open 7,495 Closed
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Pull requests list

[LowerToHW] Extract the logic related to file descriptor acquisition as a common utility function
#10288 opened Apr 21, 2026 by nanjo712 Contributor Loading…
circt-bmc: materialize debug anchors
#10287 opened Apr 21, 2026 by 5iri Contributor Loading…
[FIRRTL] Remove ReplSeqMem gating of MemToRegOfVec
#10286 opened Apr 21, 2026 by seldridge Member • Draft
1
[firtool] Fix randomization disable logic
#10285 opened Apr 21, 2026 by seldridge Member Loading…
1
[FIRRTL] Don't run MemToRegOfVec on "SeqMem"s
#10284 opened Apr 21, 2026 by seldridge Member Loading…
4
[SimToSV] support lowering stdout/stderr
#10283 opened Apr 21, 2026 by nanjo712 Contributor Loading…
2
[Synth] Add a folder/canonicalization for synth.xor_inv
#10282 opened Apr 21, 2026 by okekayode Contributor Loading…
2
[ImportVerilog] Support single-delay case for n-input prims
#10278 opened Apr 20, 2026 by TaoBi22 Contributor Loading…
3
[Synth] Add dot gate
#10277 opened Apr 20, 2026 by uenoku Member Loading…
[PyRTG] More utility methods for instructions RTG Involving the `rtg` dialect
#10272 opened Apr 19, 2026 by maerhart Member Loading…
2
[OM] Add a folder for IntegerBinaryArithmeticOp and use it in Evaluator, extend StringConcat folder
#10269 opened Apr 18, 2026 by uenoku Member Loading…
9
[OM] Introduce explicit evaluator state and op patterns
#10265 opened Apr 18, 2026 by uenoku Member • Draft
1
14
[LLHD] Run Mem2Reg per slot to fix cubic scaling LLHD
#10263 opened Apr 17, 2026 by fabianschuiki Contributor Loading…
2
[FIRRTL] LowerLayers: Do not include dummy bindfiles
#10258 opened Apr 17, 2026 by rwy7 Contributor Loading…
9
[ImportVerilog] Fix hierarchical name resolution across deduped module instances
#10255 opened Apr 17, 2026 by jpienaar Member Loading…
2
[PyRTG] Simplify instruction calls RTG Involving the `rtg` dialect
#10252 opened Apr 17, 2026 by maerhart Member Loading…
6
[LowerToHW] Avoid "assert/assume/cover" string comparison, refactor label creation, NFC
#10251 opened Apr 17, 2026 by uenoku Member Loading…
[CellIFT] Add CellIFT instrumentation pass for HW/Comb/Seq IR
#10250 opened Apr 17, 2026 by flaviens Loading…
27
[Synth] Make LowerVariadic run on any operation.
#10242 opened Apr 16, 2026 by joaovam Contributor Loading…
4
Plumb dbg.variable anchors into SMT symbol names
#10237 opened Apr 16, 2026 by 5iri Contributor Loading…
6
Add union roundtrip
#10236 opened Apr 16, 2026 by jpienaar Member Loading…
1
ImportVerilog: fix signedness propagation in ConversionExpression lowering
#10235 opened Apr 16, 2026 by kaituo-crypto Loading…
2
[Synth] Make FunctionalReduction runnable on any op
#10230 opened Apr 15, 2026 by SmitVaishnav Contributor Loading…
3
[FIRRTL][LowerLayers] Add probe type support
#10223 opened Apr 15, 2026 by prithayan Contributor Loading…
1
[Sim] Add cascade erase for print/proc.print format/get_file producer chains
#10204 opened Apr 14, 2026 by nanjo712 Contributor Loading…
4
ProTip! Exclude everything labeled bug with -label:bug.